WM7236E

8

Rev 4.0

AUDIO INTERFACE TIMING

CLK

(input)

DAT is high-impedance (hi-z) when not outputting data

DAT

(LRSEL = 1)

DAT

(LRSEL = 0)

Figure 1 Digital Microphone Interface Timing

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Digital Microphone Interface Timing

CLK cycle time

204

3333

ns

CLK duty cycle

60:40

40:60

52:48

48:52

CLK rise/fall time

6

ns

DAT enable from rising CLK edge (LRSEL = 1)

24

ns

DAT valid from rising CLK edge (LRSEL = 1)

30

80

ns

DAT disable from falling CLK edge (LRSEL = 1)

20

ns

DAT enable from falling CLK edge (LRSEL = 0)

24

ns

DAT valid from falling CLK edge (LRSEL = 0)

30

80

ns

DAT disable from rising CLK edge (LRSEL = 0)

20

ns

Notes:

1.

The DAT output is high-impedance when not outputting data; this enables the outputs of two microphones to be connected

together with the data from one microphone interleaved with the data from the other. (The microphones must be configured to

transmit on opposite channels in this case.)

2.

In a typical configuration, the Left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the Left

channel should be sampled by the receiving device on the falling CLK edge.

3.

Similarly, the Right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the Right channel

should be sampled by the receiving device on the rising CLK edge.

4.

The WM7236 operating mode is selected according to the CLK frequency

; see “Acoustic and Electrical Characteristics” for

further details.