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DS1923 Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS1923 Datasheet(HTML) 3 Page - Dallas Semiconductor |
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3 / 52 page ![]() DS1923: Hygrochron Temperature/Humidity Logger iButton with 8kB Data Log Memory 3 of 52 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO Pin, 1-Wire Write Standard speed 60 120 Overdrive speed, VPUP > 4.5V (Note 11) 6 12 Write-0 Low Time (Note 1) tW0L Overdrive speed (Note 11) 7.5 12 µs Standard speed 5 15 - e Write-1 Low Time (Notes 1, 13) tW1L Overdrive speed 1 1.95 - e µs IO Pin, 1-Wire Read Standard speed 5 15 - d Read Low Time (Notes 1, 14) tRL Overdrive speed 1 1.95 - d µs Standard speed tRL + d 15 Read Sample Time (Notes 1, 14) tMSR Overdrive speed tRL + d 1.95 µs Real-Time Clock Accuracy +25°C -3 +3 min./ month Frequency Deviation DF -20°C to +85°C -300 +60 PPM Temperature Converter 8-bit mode (Note 15) 30 75 Conversion Time tCONV 16-bit mode (11 bits) 240 600 ms Thermal Response Time Constant tRESP iButton package (Note 16) 130 s Conversion Error Without Software Correction DJ (Notes 15, 17, 18, 19) See Temperature Accuracy Graphs °C Conversion Error With Software Correction DJ (Notes 15, 17, 18, 19) See Temperature Accuracy Graphs °C Humidity Converter (Note 30) Humidity Response Time Constant tRH Slow moving air (Note 20) 30 s (Note 21) 8 12 12 bits RH Resolution 0.64 0.04 0.04 %RH RH Range (Note 22) 0 100 %RH RH Accuracy and Interchangeability With software correction (Notes 18, 19, 23, 24, 25) ±5 %RH RH Nonlinearity With software correction (Note 18) <1 RH Hysteresis (Notes 26, 27) 0.5 %RH RH Repeatability (Note 28) ±0.5 %RH Long-Term Stability At 50%RH (Note 29) <1.0 %RH/y Note 1: System requirement. Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Note 3: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2k W resistor is used to pull up the data line 2.5µs after VPUP has been applied, the parasite capacitance does not affect normal communications. Note 4: VTL, VTH are a function of the internal supply voltage. Note 5: Voltage below which, during a falling edge on IO, a logic '0' is detected. Note 6: The voltage on IO needs to be less or equal to VILMAX whenever the master drives the line low. Note 7: Voltage above which, during a rising edge on IO, a logic '1' is detected. Note 8: After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by VHY to be detected as logic '0'. Note 9: The I-V characteristic is linear for voltages less than 1V. Note 10: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached. Note 11: Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below. Note 12: Interval during the negative edge on IO at the beginning of a presence detect pulse between the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of VPUP. Note 13: e represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. Note 14: d represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. Note 15: To conserve battery power, use 8-bit temperature logging whenever possible. Note 16: This number was derived from a test conducted by Cemagref in Antony, France, in July of 2000. http://www.cemagref.fr/English/index.htm Test Report No. E42. |
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