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DM505LRBABF Datasheet(PDF) 91 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 91 Page - Texas Instruments |
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91 / 290 page  91 DM505 www.ti.com SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-6. LVCMOS DDR DC Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V VCM Input common-mode voltage VREF -1%VDDS VREF+ 1%VDDS V CPAD Pad capacitance (including package capacitance) 3 pF Differential Receiver Mode VSWING Input voltage swing DDR3/DDR3L 0.4*vdds 0.6*vdds V VCM Input common-mode voltage VREF -1%VDDS VREF+ 1%VDDS V CPAD Pad capacitance (including package capacitance) 3 pF (1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1 or vdds_ddr2). For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [10] column. (2) For more information on the I/O cell configurations (i[2:0], sr[1:0]), see Control Module section of the Device TRM. Table 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda; Balls ABF: L3, L4, L6, L5; I2C Standard Mode – 1.8 V VIH Input high-level threshold 0.7*VDDS V VIL Input low-level threshold 0.3*VDDS V Vhys Hysteresis 0.1*VDDS V II Input current at each I/O pin with an input voltage between 0.1*VDDS to 0.9*VDDS 12 µA IOZ IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 12 µA CI Input capacitance 10 pF VOL3 Output low-level threshold open-drain at 3-mA sink current 0.2*VDDS V IOLmin Low-level output current @VOL=0.2*VDDS 3 mA tOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF to 400 pF 250 ns I2C Fast Mode – 1.8 V VIH Input high-level threshold 0.7*VDDS V VIL Input low-level threshold 0.3*VDDS V Vhys Hysteresis 0.1*VDDS V II Input current at each I/O pin with an input voltage between 0.1*VDDS to 0.9*VDDS 12 µA |
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