ADCS9888 datasheet(20/34 Pages) NSC

20 / 34 page

Configuration Register Descriptions (Continued)

Address

(Hex)

Write/Read

or Read Only

Bits

POR Value

Name

Bit Name/Description

0FH

W/R

0*******

Clamp Control

Clamp Select. 0 = clamp timing determined by internal

chip counters derived from hsync. 1 = clamp timing

determined by external CLAMP signal.

*1******

CLAMP Polarity. 0 active high, 1 = active low. This bit

only has effect if Register 0FH, bit7=1.

**0*****

COAST Control COAST Select. 0 = COAST input pin is PLL coast

source. 1 = VSYNC is PLL coast source.

***0****

COAST Polarity Override. 0 = determined by chip. 1 =

determined by Register 0FH, bit 3.

****1***

COAST Polarity. 0 = active low, 1 = active high. This bit

only has an effect when Register 0FH, bit5=0,and

*****1**

Seek Override

Seek Mode Override. 0 = don’t allow low power mode.

1 = allow low power mode when sync inputs inactive. In

seek mode operation the HSOUT, VSOUT, DATACK

and DATACK, and all 48 data outputs are placed in a

high impedance state. The SOGOUT pin is still active.

The voltage references, sync detection and processing,

and serial register sub-system (for obvious reasons) are

maintained in an active state to provide a rapid

transition to normal operation.

******1*

PWRDN

Full chip power down. 0 = power down. 1 = normal

operation. In power down mode, the HSOUT, VSOUT,

DATACK, DATACK, and all 48 data outputs are placed

in a high impedance state. The SOGOUT pin is still

active. The voltage reference, sync detection and

processing, and serial register sub-system (for obvious

reasons) are maintained in an active state to provide a

rapid transition to normal operation.

10H

W/R

7:3

01111***

Sync-On-Green

Threshold

Set the voltage of the sync slicer threshold. 00H to 1FH.

LSB size is 10 mV. Setting of 00h gives a nominal

threshold of 10 mV, while maximum setting of 1FH

gives a nominal threshold of 330 mV. Optimal settings

will be lower than those used with the Analog Devices

AD9888.

*****0**

Red Clamp

Select

0 = clamp to ground. 1 = clamp to R

MIDSCV.

******0*

Blue Clamp

Select

0 = clamp to ground. 1 = clamp to B

MIDSCV.

11H

W/R

7:0

00100000

Sync Separator

Threshold

Sets how many internal 5 MHz clock periods the sync

separator will count to before toggling high or low. This

value should be set to some amount greater than the

widest expected hsync or equalization pulse width.

12H

W/R

7:0

00000000

Pre-coast

Sets the number of Hsync periods that the PLL coast

becomes active prior to Vsync. This setting is only valid

when Vsync is used as the PLL coast source.

13H

W/R

7:0

00000000

Post-Coast

Sets the number of Hsync periods that the PLL coast

stays active after Vsync becomes inactive. This setting

is only valid when Vsync is used as the PLL coast

source.

ADCS9888 Datasheet(PDF) 20 Page - National Semiconductor (TI)

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