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DM505LRBABF Datasheet(PDF) 94 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 94 Page - Texas Instruments |
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94 / 290 page  94 DM505 SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-10. LVCMOS Analog OSC Buffers DC Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION MIN NOM MAX UNIT CPAD Capacitance connected on input and output Pad on Board, CL1=CL2 12 24 pF (1) VDDS in this table stands for corresponding power supply (i.e. vdda_osc). For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [10] column. Table 5-11. LVCMOS CSI2 DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Signals MUXMODE0 : csi2_0_dx[4:0]; csi2_0_dy[4:0]; Bottom Balls: A11 / B11 / A12 / B12 / A13 / B13 / A15 / B15 / A16 / B16 MIPI D-PHY Mode Low-Power Receiver (LP-RX) VIH Input high-level voltage 880 1350 mV VIL Input low-level voltage 550 mV VITH Input high-level threshold 880 mV VITL Input low-level threshold 550 mV VHYS Input hysteresis 25 mV MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX) VIH Input high-level voltage 880 mV VIL Input low-level voltage 300 mV VITH Input high-level threshold 880 mV VITL Input low-level threshold 300 mV VHYS Input hysteresis 25 mV MIPI D-PHY Mode High-Speed Receiver (HS-RX) VIDTH Differential input high-level threshold 70 mV VIDTL Differential input low-level threshold –70 mV VIDMAX Maximum differential input voltage 270 mV VIHHS Single-ended input high voltage 460 mV VILHS Single-ended input low voltage –40 mV VCMRXDC Differential input common-mode voltage 70 330 mV ZID Differential input impedance 80 100 125 Ω (1) VITH is the voltage at which the receiver is required to detect a high state in the input signal. (2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling. (3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference between the VITH threshold and the VITL threshold. (4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state. (5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz. (6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and variations below 450 MHz. (7) This number corresponds to the VODMAX transmitter. (8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2. (9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB. (10) For more information regarding the pin name (or ball name) and corresponding signal name, see Table 4-8 CSI 2 Signal Descriptions. |
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