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ISO7763FDWR Datasheet(PDF) 22 Page - Texas Instruments |
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ISO7763FDWR Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 38 page ![]() 22 ISO7760, ISO7761 ISO7762, ISO7763 SLLSER1A – AUGUST 2017 – REVISED AUGUST 2017 www.ti.com Product Folder Links: ISO7760 ISO7761 ISO7762 ISO7763 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) See Table 2 for detailed isolation ratings. 8.3 Feature Description Table 1 lists the device features. Table 1. Device Features PART NUMBER CHANNEL DIRECTION MAXIMUM DATA RATE DEFAULT OUTPUT PACKAGE RATED ISOLATION(1) ISO7760 6 Forward, 0 Reverse 100 Mbps High DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK ISO7760 with F suffix 6 Forward, 0 Reverse 100 Mbps Low DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK ISO7761 5 Forward, 1 Reverse 100 Mbps High DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK ISO7761 with F suffix 5 Forward, 1 Reverse 100 Mbps Low DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK ISO7762 4 Forward, 2 Reverse 100 Mbps High DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK ISO7762 with F suffix 4 Forward, 2 Reverse 100 Mbps Low DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK ISO7763 3 Forward, 3 Reverse 100 Mbps High DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK ISO7763 with F suffix 3 Forward, 3 Reverse 100 Mbps Low DW-16 5000 VRMS / 8000 VPK DBQ-16 2500 VRMS / 3600 VPK 8.3.1 Electromagnetic Compatibility (EMC) Considerations Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO776x family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include: • Robust ESD protection for input and output signal pins and inter-chip bond pads. • Low-resistance connectivity of ESD cells to supply and ground pins. • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events. • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs. • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. |
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