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ADC31RF80IRMP Datasheet(PDF) 49 Page - Texas Instruments |
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ADC31RF80IRMP Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 136 page  49 ADC31RF80 www.ti.com SBAS860 – AUGUST 2017 Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table 8 shows the register configurations required to set up the absolute peak power detector. The detector operates in the fS / 8 clock domain; one peak sample is calculated over eight actual samples. The automatic gain control (AGC) modes can be configured using registers in the power-detector page (54xxh). Table 8. Registers Required for the Peak Power Detector REGISTER ADDRESS DESCRIPTION PKDET EN 5400h Enables peak detector BLKPKDET 5401h, 5402h, 5403h Sets the block length N of number of samples (S`). Number of actual ADC samples is 8x this value: N is 17 bits: 1 to 216. BLKTHHH, BLKTHHL, BLKTHLH, BLKTHLL 5407h, 5408h, 5409h, 540Ah Sets the different thresholds for the hysteresis function values from 0 to 256 (where 256 is equivalent to the peak amplitude). For example: if BLKTHHH is to –2 dBFS from peak, 10(–2 / 20) × 256 = 203, then set 5407h = CBh. DWELL 540Bh, 540Ch When the computed block peak crosses the upper thresholds BLKTHHH or BLKTHLH, the peak detector output flags are set. In order to be reset, the computed block peak must remain continuously lower than the lower threshold (BLKTHHL or BLKTHLL) for the period specified by the DWELL value. This threshold is 16 bits and is specified in terms of fS / 8 clock cycles. OUTSEL GPIO[4:1] 5432h, 5433h, 5434h, 5435h Connects the BLKPKDETH, BLKPKDETL alarms to the GPIO pins; common register. IODIR 5437h Selects the direction for the four GPIO pins; common register. RESET AGC 542Bh After configuration, reset the AGC module to start operation. |
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