X9428

Characteristics subject to change without notice.

14 of 20

REV 1.1.5 7/8/03

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HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

Note:

(8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

Input Timing

Output Timing

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

5

10

ms

Symbol

Parameter

Min.

Max.

Unit

Wiper response time after the third (last) power supply is stable

10

µs

Wiper response time after instruction issued (all load instructions)

10

µs

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

10

µs

SCL

SDA

(START)

(STOP)

SCL

SDA

SCL

SDA