4K x 16/18 and 8K x 16/18 Dual-Port
Static RAM with SEM, INT, BUSY
CY7C024/0241
CY7C025/0251
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06035 Rev. *B
Revised June 22, 2004
Features
• True Dual-Ported memory cells which allow
simultaneous reads of the same memory location
• 4K x 16 organization (CY7C024)
• 4K x 18 organization (CY7C0241)
• 8K x 16 organization (CY7C025)
• 8K x 18 organization (CY7C0251)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 150 mA (typ.)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Available in 84-pin PLCC and 100-pin TQFP
Functional Description
The CY7C024/0241 and CY7C025/0251 are low-power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Var-
ious arbitration schemes are included on the CY7C024/0241
and CY7C025/0251 to handle situations when multiple pro-
cessors access the same piece of data. Two ports are provid-
ed, permitting independent, asynchronous access for reads
and writes to any location in memory. The CY7C024/0241 and
CY7C025/0251 can be utilized as standalone 16-/18-bit du-
al-port static RAMs or multiple devices can be combined in
order to function as a 32-/36-bit or wider master/slave du-
al-port static RAM. An M/S pin is provided for implementing
32-/36-bit or wider memory applications without the need for
separate master and slave devices or additional discrete logic.
Application areas include interprocessor/multiprocessor de-
signs, communications status buffering, and dual-port vid-
eo/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being accessed by
the other port. The Interrupt Flag (INT) permits communication be-
tween ports or systems by means of a mail box. The semaphores are
used to pass a flag, or token, from one port to the other to indicate that
a shared resource is in use. The semaphore logic is comprised of
eight shared latches. Only one side can control the latch (semaphore)
at any time. Control of a semaphore indicates that a shared resource
is in use. An automatic power-down feature is controlled indepen-
dently on each port by a chip select (CE) pin.
The CY7C024/0241 and CY7C025/0251 are available in
84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin
Thin Quad Plastic Flatpack (TQFP).
v
7C024–1
R/WL
UBL
LB L
CE L
OEL
A0L
R/WR
UBR
CE R
OE R
CE L
OE L
UB L
UB R
I/O 8L –I/O 15L
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
SEM L
SEM R
BUSYL
INT L
INTR
M/S
CONTROL
I/O
LB L
LB R
I/O 0L –I/O 7L
R/W L
R/W R
LB
R
CE
R
OE R
A0R
I/O8R I/O15R
BUSYR
I/O 0R I/O 7R
(CY7C025/0251)
A12L
A12R (CY7C025/0251)
[1]
[1]
Logic Block Diagram
–
–
ADDRESS
DECODER
A11L
A11R
[2]
[3]
[2]
[3]
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