AD4002 datasheet(19/36 Pages) AD

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Preliminary Technical Data

AD4002/AD4006/AD4010

Rev. PrA | Page 19 of 36

APPLICATIONS INFORMATION

TYPICAL APPLICATION DIAGRAMS

Figure 33 shows an example of the recommended connection

diagram for the AD4002/AD4006/AD4010 when multiple

supplies are available. This configuration is used for best

performance because the amplifier supplies can be selected to

allow the maximum signal range.

Figure 34 shows a recommended connection diagram when

using a single-supply system. This setup is preferable when only

a limited number of rails are available in the system and power

dissipation is of critical importance.

V+

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4002/

AD4006/

AD40102

3-WIRE/4-WIRE

INTERFACE

1.8V

1.8V TO 5V

V+

≥ +6.5V

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

V–

≤ –0.5V

HOST

SUPPLY

100nF

V–

AMP

VREF

VCM = VREF/2

REF1

LDO

AMP

VCM = VREF/2

10µF

10kΩ

Figure 33. Typical Application Diagram with Multiple Supplies

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4002/

AD4006/

AD40102

1.8V

1.8V TO 5V

V+ = 5V

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

HOST

SUPPLY

100nF

4.096V

AMP

0.9 × VREF

0.1 × VREF

VCM = VREF/2

REF1

LDO

AMP

VCM = VREF/2

10µF1

10kΩ

3-WIRE/4-WIRE

INTERFACE

1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).

2SPAN COMPRESSION MODE ENABLED.

3SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION.

Figure 34. Typical Application Diagram with a Single Supply

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