AD7616-PBSTZ datasheet(13/47 Pages) AD

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AD7616-P

Data Sheet

Rev. 0 | Page 12 of 46

Pin No.

Type1

Mnemonic2

Description

53 to 60

DO/DI

DB8 to DB15

Parallel Output/Input Data Bit 8 to Data Bit 15. These pins act as three-state parallel digital

input/outputs. Refer to the Parallel Interface section for further details.

WR/BURST

Write/Burst Mode Enable.

In software mode, this pin acts as WR for register write commands.

In hardware mode, this pin enables burst mode. The signal state is latched on the release of a

full reset, and requires an additional full reset to reconfigure. Refer to the Burst Sequencer section

for further information.

Parallel Data Read Control Input. When both CS and RD are logic low in parallel mode, the

output bus is enabled.

Chip Select. This active low logic input frames the data transfer. When both CS and RD are

logic low, the DBx output bus is enabled and the conversion result is output on the parallel

data bus lines.

64 to 66

CHSEL0 to

CHSEL2

Channel Selection Input 0 to Input 2 (Hardware Mode Only). In hardware mode, these inputs

select the input channels for the next conversion in ADC A and ADC B. For example, CHSELx =

0x000 selects V0A and V0B for the next conversion; CHSELx = 0x001 selects V1A and V1B for

the next conversion.

BUSY

Busy Output. This pin transitions to a logic high after a CONVST rising edge and indicates that

the conversion process started. The BUSY output remains high until the conversion process

for the current selected channels is complete. The falling edge of BUSY signals that the

conversion data is being latched into the output data registers and is available to read. Data

must be read after BUSY returns to low. Rising edges on CONVST have no effect while the

BUSY signal is high.

CONVST

Conversion Start Input for ADC A and ADC B. This logic input initiates conversions on the

analog input channels.

A conversion is initiated when CONVST transitions from low to high for the selected analog

input pair. When burst mode and oversampling mode are disabled, every CONVST transition

from low to high converts one channel pair. In sequencer mode, when burst mode or

oversampling is enabled, a single CONVST transition from low to high is necessary to perform

the required number of conversions.

GND

REGGND

Internal Analog Regulator Ground. This pin must connect to the AGND plane of a system.

CAP

REGCAP

Decoupling Capacitor Pin for Voltage Output from Internal Analog Regulator. Decouple this

output pin separately to REGGND using a 10 μF capacitor. The voltage at this pin is 1.87 V

typical.

V0B

Analog Input Channel 0, ADC B.

AI GND

V0BGND

Analog Input Ground for V0B.

V1B

Analog Input Channel 1, ADC B.

AI GND

V1BGND

Analog Input Ground for V1B.

V2B

Analog Input Channel 2, ADC B.

AI GND

V2BGND

Analog Input Ground for V2B.

V3B

Analog Input Channel 3, ADC B.

AI GND

V3BGND

Analog Input Ground for V3B.

1 AI is analog input, GND is ground, P is power supply, CAP is decoupling capacitor pin, REF is reference input/output, DI is digital input, and DO is digital output.

2 Note that throughout this data sheet, multifunction pins, such as WR/BURST, are referred to either by the entire pin name or by a single function of the pin, for

example, WR, when only that function is relevant.

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