AD7616-PBSTZ datasheet(27/47 Pages) AD

27 / 47 page

AD7616-P

Data Sheet

Rev. 0 | Page 26 of 46

SOFTWARE MODE

If software mode is selected and the reference is configured, all

other configuration settings in the AD7616-P are controlled via

the on-chip registers. All functionality of the AD7616-P is

available when software mode is selected. Table 10 provides a

summary of the signals that are latched by the device on the release

of a full reset, depending on the mode of operation chosen.

RESET FUNCTIONALITY

The AD7616-P has two reset modes: full or partial. The reset

mode selected is dependent on the length of the reset low pulse.

A partial reset requires the RESET pin to be held low between

40 ns and 500 ns. After 120 ns from the release of RESET, the

device is fully functional and a conversion can be initiated. A

full reset requires the RESET pin to be held low for a minimum

of 1.2 µs. After 15 ms from the release of RESET, the device is

completely reconfigured and a conversion can be initiated.

A partial reset reinitializes the following modules:

•

Sequencer

•

Digital filter

•

Both SAR ADCs

The current conversion result is discarded on completion of a

partial reset. The partial reset does not affect the register values

programmed in software mode or the latches that store the user

configuration in both hardware and software modes. A dummy

conversion is required in software mode after a partial reset.

A full reset returns the device to its default power-on state. The

following features are configured when the AD7616-P is

released from full reset:

•

Hardware mode or software mode

•

Internal/external reference

•

Interface type

On power-up, the RESET signal can be released as soon as both

the VCC and VDRIVE supplies are stable. The logic level of the

HW_RNGSELx, REFSEL, and PAR pins when the RESET pin is

released after a full reset determines the configuration.

If hardware mode is selected, the functionality determined by

the BURST and SEQEN signals is also latched when the RESET

pin transitions from low to high in full reset mode, as shown in

Figure 3. After the functionality is configured, changes to these

signals are ignored. In hardware mode, the analog input range

(HW_RNGSELx signals) can be configured during a full reset, a

partial reset, or during normal operation, but hardware/software

mode selection requires a full reset to reconfigure when latched.

In hardware mode, the CHSELx and HW_RNGSELx pins are

read upon release of a full or partial reset to perform the following

actions:

•

Determine the initial analog input channel pair to acquire

for conversion.

•

Configure the initial settings for the sequencer.

•

Select the analog input voltage range.

The CHSELx and HW_RNGSELx signals are not latched. The

channel pair selected for conversion, or the hardware sequencer,

can be reconfigured during normal operation by setting and

maintaining the CHSELx signal level before the CONVST rising

edge, and ensuring the signal level remains constant until after

BUSY transitions low again. See the Channel Selection section

for further details.

In software mode, all additional functionality is configured by

controlling the on-chip registers.

PIN FUNCTION OVERVIEW

There are several dual-function pins on the AD7616-P. Their

functionality is dependent on the mode of operation selected by

the HW_RNGSELx pins. Table 11 outlines the pin functionality

in the different modes of operation and interface modes.

Table 11. Pin Functionality Overview

Pins

Operation Mode

Software

(HW_RNGSELx = 00)

Hardware

(HW_RNGSELx ≠ 00)

CHSELx

No function, connect

to DGND

CHSELx

WR/BURST

BURST

DB15 to DB0

HW_RNGSELx

HW_RNGSELx,

connect to DGND

HW_RNGSELx, configure

analog input range

SEQEN

No function, connect

to DGND

SEQEN

REFSEL

AD7616-PBSTZ Datasheet(PDF) 27 Page - Analog Devices

AD7616-PBSTZ Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL