AD7761BSTZ datasheet(35/76 Pages) AD

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AD7761

Data Sheet

Rev. A | Page 34 of 75

Table 18. MODEx Selection Details: Pin Control Mode

Mode Hex.

MODE3

MODE2

MODE1

MODE0

Power Mode

DCLK Frequency

Data Conversion

0x0

Low power

MCLK/1

Standard

0x1

Low power

MCLK/2

Standard

0x2

Low power

MCLK/4

Standard

0x3

Low power

MCLK/8

Standard

0x4

Median

MCLK/1

Standard

0x5

Median

MCLK/2

Standard

0x6

Median

MCLK/4

Standard

0x7

Median

MCLK/8

Standard

0x8

Fast

MCLK/1

Standard

0x9

Fast

MCLK/2

Standard

0xA

Fast

MCLK/4

Standard

0xB

Fast

MCLK/8

Standard

0xC

Low power

MCLK/1

One-shot

0xD

Median

MCLK/1

One-shot

0xE

Fast

MCLK/2

One-shot

0xF

Fast

MCLK/1

One-shot

Table 19. MODEx Example Selection

Mode Hex

MODE3

MODE2

MODE1

MODE0

Power Mode

DCLK Frequency

Data Conversion

0x3

Low Power

MCLK/8

Standard

Configuration Example

In the example shown in Table 19, the lowest current

consumption is used, and the AD7761 is connected to an FPGA.

The FORMATx pins are set such that all eight data outputs,

DOUT0 to DOUT7, connect to the FPGA. For the lowest

power, the lowest DCLK frequency is used. The input bandwidth

is set through the combination of selecting decimation by 64

and selecting the wideband filter.

ODR = fMOD ÷ Decimation Ratio

where:

fMOD is MCLK/32 for low power mode (see Table 17).

Decimation Ratio = 64.

Thus, for this example, where MCLK = 32.768 MHz,

ODR = (32.768 MHz/32) ÷ 64 = 16 kHz

Minimizing the DCLK frequency means selecting DCLK =

MCLK/8, which results in a 4 MHz DCLK signal. The period of

DCLK in this case is 1/4 MHz = 250 ns. The data conversion on

each DOUTx pin is 24 bits long. The conversion data takes 24 ×

250 ns = 6 μs to be output. All 24 bits must be output within the

ODR period of 1/16 kHz, which is approximately 64 μs. In this

case, the 6 μs required to read out the conversion data is well

within the 64 μs between conversion outputs. Therefore, this

combination, which is summarized in Table 19, is viable for use.

Channel Standby

Table 20 shows how the user can put channels into standby mode.

Set either ST0 or ST1 to Logic 1 to place banks of four channels

into standby mode. When in standby mode, the disabled channels

hold their position in the output data stream. The 8-bit header

and 16-bit conversion results are set to all zeros when the ADC

channels are set to standby.

The VCM voltage output is associated with the Channel 0

circuitry. If Channel 0 is put into standby mode, the VCM

voltage output is also disabled for maximum power savings.

Channel 0 must be enabled while VCM is being used externally

to the AD7761.

The crystal excitation circuitry is associated with the Channel 4

circuitry. If Channel 4 is put into standby mode, the crystal

circuitry is also disabled for maximum power savings. Channel 4

must be enabled while the external crystal is used on the AD7761.

Table 20. Truth Table for the AD7761 ST0 and ST1 Pins

ST1

ST0

Function

All channels operational.

Channel 0 to Channel 3 in

standby. Channel 4 to

Channel 7 operational.

Channel 4 to Channel 7 in

standby. Channel 0 to

Channel 3 operational.

All channels in standby.

AD7761BSTZ Datasheet(PDF) 35 Page - Analog Devices

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