AD6652PCB datasheet(26/76 Pages) AD

26 / 76 page

AD6652

Rev. 0 | Page 26 of 76

he reference into four possible

REF

ce configurations, REFT and REFB drive the A/D

put span. The input range of

oltage at the reference pin for

re not

shown.

lting VREF

Internal Reference Connection

652 detects the potential at the

In all referen

A comparator within the AD6

SENSE pin and configures t

states, which are summarized in Table 11. If SENSE is grounde

the reference amplifier switch is connected to the internal

resistor divider (see Figure 40), setting VREF to a FIXED 1 V

reference output. Connecting the SENSE pin directly to V

switches the reference amplifier output to the SENSE pin,

completing the loop and providing a fixed 0.5 V reference

output. If a resistor divider is connected, as shown in Figure 41,

the switch is again set to the SENSE pin. This puts the reference

amplifier in a noninverting mode with the VREF programmab

output defined as follows:

VREF = 0.5 × (1 + R2/R1)

conversion core and establish its in

the ADC always equals twice the v

either an internal or an external reference.

The reference amplifier switch is located near the bottom left.

The SENSE pin is shown connected to ground, which sets VREF

to 1 V. Decoupling capacitors must be duplicated for the

Channel B ADC core, if it is used. The Channel B ref amp an

ADC core are identical to those of Channel A, but a

Table 11. Reference SENSE Operation

Selected Mode

SENSE Voltage

Resu

(V)

Resulting Differential Span (V p-p)

External Reference

AVDD

External Reference

2 × External Reference

Internal Fixed Reference

VREF

0.5

1.0

Programmable Reference

0.2 V to VREF

0.5 × (1 + R2/R1)

2 × VREF (See Figure 42)

Internal Fixed Reference

AGND to 0.2 V

1.0

2.0

VINA+

VINA–

REFT_A

VREF

TO CH B

REF AMP

SELECT

CORE

REFB_A

0.5V

0.1

µF

SENSE

LOGIC

CH A

ADC

0.1

µF

REF

AMP A

0.1

µF

RINT

0.1

µF

RINT

Figure 40. Fixed Internal Reference Configuration

VINA+

VINA–

REFT_A

VREF

TO CH B

REF AMP

REF

AMP A

CH A

ADC

CORE

REFB_A

0.1

µF

0.1

µF

VREF

0.5V

0.1 F

0.1

µF

RINT

SENSE

SELECT

LOGIC

RINT

WHERE R1 + R2 =

10k

Ω TO 20kΩ

Figure 41. Programmable Reference Configuration

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