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LED171596ARSLR Datasheet(PDF) 34 Page - Texas Instruments |
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LED171596ARSLR Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 153 page  34 LED171596A SNVSAY2 – OCTOBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table 11. STATUS Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h 2 slope_matrix_busy R 0h Matrix sloper status 0 - Matrix sloper ready 1 - Matrix sloper busy 1 slope_master_busy R 0h Master sloper status 0 - Master sloper ready 1 - Master sloper busy 0 latch_busy R 0h SRAM data latching status 0 - SRAM data latching ready 1 - SRAM data latching busy 7.6.1.5 INT_STATUS Register (Address = 4h) [reset = 0h] INT_STATUS is shown in Figure 30 and described in Table 12. Return to Summary Table. Interrupt status bits are set by events and cleared by bits in INT_CLEAR register. Status bits show if an event has occurred since the last clearing. Start of an unmasked event sets the INT pin. If INT pin is cleared while an event is active, it stays cleared until some other event starts. Figure 30. INT_STATUS Register 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED led_open led_short RESERVED tsd slope_matrix_d one slope_master_d one latch_done R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 12. INT_STATUS Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6 led_open R 0h LED open fault interrupt status 5 led_short R 0h LED short fault interrupt status 4 RESERVED R 0h 3 tsd R 0h Thermal shutdown interrupt status 2 slope_matrix_done R 0h Matrix sloper interrupt status 1 slope_master_done R 0h Master sloper interrupt status 0 latch_done R 0h SRAM latching interrupt status 7.6.1.6 INT_MASK Register (Address = 5h) [reset = 17h] INT_MASK is shown in Figure 31 and described in Table 13. Return to Summary Table. Interrupt mask bits mask the event for INT pin. Interrupt status bits are not affected by mask bits. |
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