VSP5000

SLES057 – DECEMBER 2002

www.ti.com

2

Thesedevices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PRODUCT

PACKAGE

PACKAGE

OUTLINE

DESIGNATOR(1)

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

VSP5000

64 Lead LQFP

PM

25

°Cto85°C

VSP5000PM

VSP5000PM

Tray

VSP5000

64-Lead LQFP

PM

–25

°C to 85°C

VSP5000PM

VSP5000PMR

Tape and reel

(1) A detailed drawing and a dimension table are located at the end of the data sheet.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

UNITS

Supply voltage, VCC, VDD

4 V

Supply voltage differences, among VCC terminals

±0.1 V

Ground voltage differences, AGND, DGND

±0.1 V

Digital input voltage

–0.3 V to VDD + 0.3 V

Analog input voltage

–0.3 V to VCC + 0.3 V

Input current (any leads except supplies)

±10 mA

Ambient temperature under bias

–40

°C to 125°C

Storage temperature

–55

°C to 150°C

Junction temperature

150

°C

Lead temperature (soldering, 5 sec)

260

°C

Package temperature (IR reflow, peak)

250

°C

(1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

all specifications at TA = 25°C, all power supply voltages = 3.3 V, and conversion rate (fADCCK) = 30 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VSP5000

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

12

Bits

Signal pass

2

ch

Maximum conversion rate

30

MHz

DIGITAL INPUTS

VT+

Input low-to-high threshold voltage

1.8

V

VT–

Input high-to-low threshold voltage

1.1

V

IIH

Input logic high current

VI = 3 V

±20

µA

IIL

Input logic low current

VI = 0 V

±20

µA

Input limit

–0.3

VCC+0.3

SYSCLK clock duty cycle

50%

Input capacitance

5

pF

DIGITAL OUTPUTS (even and odd channels)

Logic coding

Straight binary

Multiplex frequency

60

MHz

VOH

Output logic high voltage

IOH = –2 mA

2.5

V

VOL

Output logic low voltage

IOL = 2 mA

0.4

V