VSP5000 datasheet(13/19 Pages) BURR-BROWN

13 / 19 page

VSP5000

SLES057 – DECEMBER 2002

www.ti.com

At the sampling for the OB pixel and effective pixel, VCLAMP voltage is charged to capacitor C1. The voltage lower than

VCLAMP, according to the signal voltage from the CCD, is charged to capacitor C2. As the voltage difference in C1 and C2

is acquired at the hold period, the signals from the CCD are acquired as the voltage based on VCLAMP.

In the CDS mode, signal voltage takes as voltage difference between sampled voltage by SHP (reference level) and SHD

(data level), the signal level is not affected, even when VCLAMP changes or fluctuates in some degree due to leakage, etc.

However, when operated as SH, VCLAMP fluctuation causes an offset error, because the signal is acquired based on

VCLAMP. In order to prevent VCLAMP leakage, a buffer is inserted to input in the SH mode.

–

INPUTCLP

VSP5000

OPA

C1 = 10 pF

C2 = 10 pF

SHD

CCDIN

SHD

VCLAMP

CIN

CCD Output

VCLAMP

Figure 2. Simplified Sample Hold (SH) Circuit

INPUT CLAMP (DUMMY PIXEL CLAMP)

Output from the CCD image sensor is ac-coupled with the VSP5000 device through a capacitor. The input clamp

reproduces the dc bias lost by ac-coupling and supplies optimum dc bias for proper operation of the CDS/SH circuit.

Simplified block diagrams of the input clamp circuit are shown in Figure 1 and Figure 2.

The input signal level is clamped to the internal reference voltage by activating both SHP (when at CDS mode or SHD when

at SH mode) and INPUTCLP during the CCD dummy pixel output period.

HIGH PERFORMANCE ANALOG-TO-DIGITAL CONVERTER (ADC)

The analog-to-digital converter of the VSP5000 device is composed of pipeline architecture. The ADC converter has

complete differential circuit configuration, error correction circuit, and 14-bit resolution is assured.

Circuits which generate the necessary reference voltage at the ADC are built inside the device and are shown as REFP

(high-potential reference), REFN (low-potential reference), and CM (common-mode voltage) terminals outside the device.

In order to assure ADC accuracy, these reference voltage terminals need to be sufficiently decoupled by capacitors.

DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA)

The digital programmable gain amplifier (DPGA) circuit controls the gain value in the range of 0 fold to 16 fold (24 dB) by

inputting the digital code through the serial interface. See the serial interface section for details. Gain changes linearly in

proportion to the setting code.

VSP5000 Datasheet(PDF) 13 Page - Burr-Brown (TI)