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ST92F120 Datasheet(PDF) 45 Page - STMicroelectronics |
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ST92F120 Datasheet(HTML) 45 Page - STMicroelectronics |
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45 / 324 page ![]() 45/324 ST92F120 - SINGLE VOLTAGE FLASH & EEPROM REGISTER DESCRIPTION (Cont’d) 3.3.2 Status Registers During a Flash or an EEPROM write operation any attempt to read the memory under modification will output invalid data (FFh equivalent to a NOP in- struction). This means that the Flash memory is not fetchable when a write operation is active: the write operation commands must be given from an- other memory (EEPROM, internal RAM, or exter- nal memory). Two Status Registers (FESR[1:0] are available to check the status of the current write operation in Flash and EEPROM memories. FLASH & EEPROM STATUS REGISTER 0 (FESR0) Address: 224002h -Read/Write Reset value: 0000 0000 (00h) Bit 7 = FEERR: Flash or EEPROM write ERRor (Read/Write). This bit is set by hardware when an error occurs during a Flash or an EEPROM write operation. It must be cleared by software. 0: Write OK 1: Flash or EEPROM write error Bits 6:0 = FESS[6:0]. Flash and EEPROM Status Sector 6-0 (Read Only). These bits are set by hardware and give the status of the 7 Flash and EEPROM sectors (TF, E1, E0, F3, F2, F1, F0). The meaning of FESSx bit for sec- tor x is given by the following table: FLASH & EEPROM STATUS REGISTER 1 (FESR1) Address: 224003h -Read Only Reset value: 0000 0000 (00h) Bit 7 = ERER. Erase error (Read Only). This bit is set by hardware when an Erase error oc- curs during a Flash or an EEPROM write opera- tion. This error is due to a real failure of a Flash cell, that can not be erased anymore. This kind of error is fatal and the sector where it occurred must be discarded (if it was in one of the EEPROM sec- tors, the hardware emulation can not be used any- more). This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by soft- ware. 0: Erase OK 1: Erase error Bit 6 = PGER. Program error (Read Only). This bit is automatically set when a Program error occurs during a Flash or an EEPROM write opera- tion. This error is due to a real failure of a Flash cell, that can not be programmed anymore. The byte where this error occurred must be discarded (if it was in the EEPROM memory, the byte must be reprogrammed to FFh and then discarded, to avoid the error occurring again when that byte is internally moved). This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by software. 0: Program OK 1: Flash or EEPROM Programming error 76 54 321 0 FEER R FESS 6 FESS 5 FESS 4 FESS 3 FESS 2 FESS 1 FESS 0 Table 9. FESSx bit Values FEERR FBUSY EBUSY FSUSP FESSx=1 meaning 1- - Write Error in Sector x 01 - Write operation on-going in sec- tor x 001 Sector Erase Suspended in sector x 000 Don’t care 7 654 32 10 ERER PGER SWE R Table 9. FESSx bit Values FEERR FBUSY EBUSY FSUSP FESSx=1 meaning 9 |
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