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ADAV803

Rev. A | Page 53 of 60

PLL Control Register 1—Address 1110100 (0x74)

Table 128. PLL Control Register 1 Bit Map

DIRIN_CLK1

DIRIN_CLK0

MCLKODIV

PLLDIV

PLL2PD

PLL1PD

XTLPD

SYSCLK3

Table 129. PLL Control Register 1 Bit Descriptions

Bit Name

Description

DIRIN_CLK[1:0]

Recovered S/PDIF clock sent to SYSCLK3.

00 = SYSCLK3 comes from PLL block.

01 = Reserved.

10 = Reserved.

11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN.

MCLKODIV

Divide input MCLK by 2 to generate MCLKO.

0 = Disabled.

1 = Enabled.

PLLDIV

Divide XIN by 2 to generate the PLL master clock.

0 = Disabled.

1 = Enabled.

PLL2PD

Power-down PLL2.

0 = Normal.

1 = Power-down.

PLL1PD

Power-down PLL1.

0 = Normal.

1 = Power-down.

XTLPD

Power-down XTAL oscillator.

0 = Normal.

1 = Power-down.

SYSCLK3

Clock output for SYSCLK3.

0 = 512 × fS.

1 = 256 × fS.

ADAV803 Datasheet(PDF) 54 Page - Analog Devices

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