ADC10D040 datasheet(9/28 Pages) NSC

9 / 28 page

Converter Electrical Characteristics (Continued)

The following specifications apply for V

A =VD = +3.3 VDC,VDR = +2.5 VDC,VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN

(a.c. coupled) = FSR = 1.4 V

P-P,CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS =50

Ω,t

rc =tfc < 4 ns, NOT offset cor-

rected. Boldface limits apply for T

A =TMIN to TMAX: all other limits TA = 25˚C (Note 7).

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

Digital Supply Current

PD = LOW, STBY = LOW, d.c. input

mA (max)

PD = LOW, STBY = HIGH

0.1

PD = HIGH, STBY = LOW or HIGH

0.1

Digital Output Driver Supply

Current (Note 10)

PD = STBY = LOW, dc input

1.9

2.5

mA (max)

Power Consumption

PD = LOW, STBY = LOW, d.c. input

267

305

mW (max)

PD = LOW, STBY = LOW, 1 MHz Input

270

PD = LOW, STBY = HIGH

PD = HIGH, STBY = LOW or HIGH

0.6

PSRR1 Power Supply Rejection Ratio

Change in Full Scale with 3.0V to 3.6V Supply

Change

PSRR2 Power Supply Rejection Ratio

Rejection at output with 10.3 MHz, 250 mV

P-P

Riding on V

A and VD

AC Electrical Characteristics

OS = Low (Multiplexed Mode)

The following specifications apply for V

A =VD = +3.3 VDC,VDR = +2.5VDC,VREF = 1.4 VDC, GAIN = OF = 0V, OS = 0V, VIN

(a.c. coupled) = FSR = 1.4 V

P-P,CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS =50

Ω,t

rc =tfc < 4 ns, NOT offset cor-

rected. Boldface limits apply for T

A =TMIN to TMAX: all other limits TA = 25˚C (Note 7)

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 9)

Units

(Limits)

CLK1

Maximum Clock Frequency

MHz (min)

CLK2

Minimum Clock Frequency

MHz

Duty Cycle

% (min)

% (max)

Pipeline Delay (Latency)

I Data

2.5

Clock Cycles

Q Data

3.0

Clock Cycles

r,tf

Output Rise and Fall Times

Offset Correction Pulse Width

ns (min)

Output Delay from CLK Edge to

Data Valid

ns (max)

DIQ

I/Q Output Delay

SKEW

I/Q to Data Skew

±200

Sampling (Aperture) Delay

2.2

Aperture Jitter

<10

ps (rms)

VALID

Data Valid Time

7.5

Overrange Recovery Time

Differential V

IN step from 1.5V to

WUPD

PD Low to 1/2 LSB Accurate

Conversion (Wake-Up Time)

<1ms

WUSB

STBY Low to 1/2 LSB Accurate

Conversion (Wake-Up Time)

800

ADC10D040 Datasheet(PDF) 9 Page - National Semiconductor (TI)

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