MFC2000 datasheet(89/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-59

4.5.1.5

Power Down Mode

When the ASIC is powered down, the DRAMs cannot be accessed. Only DRAM refresh will continue on battery

power (VDRAM). Refresh timing is generated from a one shot and an internal gate delay circuit during battery

powered operation. To ensure a smooth transition from VDD refresh to battery powered refresh, a control signal

from the power reset block allows the DRAM controller to switch from VDD refresh to battery refresh when power

is down. When the prime power is reapplied, the refresh logic switches back to VDD refresh. The refresh speed

selected using the BackupConfig register remains in force during the battery backed up mode. The DRAM

Backup time duration is defined by the two DRAM Backup time bits in the BackupConfig register. No backup, 1-2

days, 2-3 days, and infinite are the backup options.

Note:

The AMFPC ASIC uses a 3V process; therefore, if the DRAM memory structure is to be

backed up, for the lowest power consumption 3 DRAMs should be used. Also, any external

circuitry must also be battery powered. The output pads of the AMFPC are only 5V tolerant

during high Z. The simplified block diagram for the DRAM controller is illustrated in Figure 4-16.

SIU

DRAM CONTROLLER

BATTERY BACKED UP LOGIC

DRAM STATE

MACHINE

MUX

REFRESH

SPEED

RASn[1:0]

CASOn[1:0]

DWRn

DRAM CONTROL

ONESHOT

SIUCLK

DRAMREQ

DRAMRDY

DRAM CNTL.

DRAM ADDR

EXTERNAL ADDRESS

DATABUS

OSCCLK,

CO_1DAY

SIU CNTL

SWITCH

BATTERY

BACKUP

CASEn[1:0]

DOEOn

DOEEn

DRAM STATE

MACHINE

BANK 0

BANK 1

RTC Battery

DRAM Battery

Figure 4-16. Simplified DRAM Controller Block Diagram

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