MFC2000 datasheet(91/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-61

4.5.2

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

DRAM Control

(DRAMCtrl1)

$01FF8821

Bank 1 Address Multiplexing

Bank 1

Increase

RAS Cycle

Time

Bank 1

2-cycle

RAS

Precharge

Bank 1

1-cycle

RAH

Bank 1 Non-interleaved

Speed Control

00 = Fast Mode

01 = Normal Mode

10 = Slow Mode

11 = N/A

Rst. Value

x0000000b

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

DRAM Control

(DRAMCtrl1)

$01FF8820

Bank 0 Address Multiplexing

Bank 0

Increase

RAS Cycle

Time

Bank 0

2-cycle

RAS

Precharge

Bank 0

1-cycle

RAH

Bank 0 Non-interleaved

Speed Control

00 = Fast Mode

01 = Normal Mode

10 = Slow Mode

11 = N/A

Rst. Value

x0000000b

Read Value

00h

operation that is desired.

Bits 15-13: Bank 1 Address Multiplexing

This register controls the addressing multiplexing for Bank 1

Bit 12:

Bank 1 Increase RAS Cycle Time

This register will add one cycle after the refresh cycle prior to RAS

precharge to meet TRC (RASn cycle time). This is needed in order to

use 70 ns DRAMs while running at 39MHz.

Bit 11:

Bank 1 2-cycle RAS Precharge

This register will increase the RASn[1] Precharge time from 1 to 2

clock cycles.

Bit 10:

Bank 1 1-cycle RAH

This register will increase the RASn[1] address hold time. When this

bit is set, the address will be multiplexed 1 clock cycle after the falling

edge of RAS[1]n. The default setting will multiplex the row/column

address ½ clock cycle after the falling edge of RAS[1]n.

Bit 9-8:

Bank 1 Speed Control

These registers will control the speed of the DRAM interface for bank

1 when in the non-interleaved mode. This register controls the width of

the CASn signal. These bits are ignored in interleaved mode.

Bit 9

Bit 8

Non-Interleaved Operation:

CASn is ½ clock cycle wide.

CASn is 1 clock cycle wide.

CASn is 2 clock cycles wide for Read

and 1 clock cycle wide for write.

N/A

Bits 7-5:

Bank 0 Addressing Multiplexing:

This register controls the addressing multiplexing for Bank 0

(Table 4-12).

MFC2000 Datasheet(PDF) 91 Page - List of Unclassifed Manufacturers

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