MFC2000 datasheet(109/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-79

4.7.2

DMA Operation and Timing

The DMA controller arbitrates DMA requests from all sources (internal and external), and then acknowledges the

request of the source with the highest priority at the start of the next bus cycle. After each request has been

issued, the associated acknowledge signal is activated with a minimum delay of 2 internal clock cycles. The

maximum delay is dependent on both the number of pending higher priority DMA requests, and the length of the

associated bus cycles (including wait states and halt states due to DMA to DRAM and refresh cycle collisions).

The DMA controller informs the bus control logic (SIU), and provides the address and read/write signal prior to the

next bus cycle. At the time of the next bus cycle, the SIU routes the address and data onto the proper bus. If the

external bus is required to complete the DMA transfer, the DMA controller notifies the external bus control logic,

which in turn halts the CPU. After the completion of a DMA cycle, the DMA controller increments or decrements

the DMA address counter.

A non-maskable interrupt (SYSIRQ) to the CPU allows the active DMA to be completed, but locks-out all other

DMA acknowledge signals in the event of a power down condition.

DMA Channel 3 address progression is controlled by the Bit Rotation logic and is not effected by the DMA

acknowledges like other channels. The Bit Rotation Logic provides an address progression value, an increment/

decrement (add/subtract) control and a count strobe. When the strobe is held active during the rising edge of the

siuclk, the progression value is either added or subtracted from the current address value. Below is a table

showing the control bit assignments.

Table 4-18 DMA Channel 3 Control Bit Assignment

Count Control Assignments

countcntl(11)

Count Strobe

countcntl(10)

Dec_Incn

countcntl(9)

Cnt_By_32k

Add_value(15)

countcntl(8)

Cnt_By_16k

Add_value(14)

countcntl(7)

Cnt_By_8192

Add_value(13)

countcntl(6)

Cnt_By_4096

Add_value(12)

countcntl(5)

Cnt_By_2048

Add_value(11)

countcntl(4)

Cnt_By_1024

Add_value(10)

countcntl(3)

Cnt_By_512

Add_value(9)

countcntl(2)

Cnt_By_4

Add_value(2)

countcntl(1)

Cnt_By_2

Add_value(1)

countcntl(0)

Cnt_By_1

Add_value(0)

4.7.3

Timing

4.7.3.1

Internal DMA Requests

DMA requests are sourced by sub-blocks or peripherals within the ASIC or by an external device (Ch 0 or 1).

Some logic blocks may source multiple DMA request lines. For example, the T4 Logic requires 3 request lines:

input data, reference data and output data. These sources will issue DMA request signals, and the sequential

access indicator, synchronized to the rising edge of SIUCLK. During the bus cycle that the requests are received,

the controller will inform the SIU that the next bus cycle will be a DMA cycle. The DMA controller also provides the

address, the sequencial access, and read/write control information to the SIU. The SIU will then activate the DMA

bus acknowledge signal when the DMA controller becomes the bus master. On the first rising edge of the SIUCLK

after the DMA bus acknowledge signal becomes active, the peripheral DMA acknowledge to the requesting

peripheral will be set high indicating the start of the DMA cycle. For a DMA single cycle write, the requesting

device must drive data onto the bus during activation of the peripheral DMA acknowledge signal. And for a single

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