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AD6642EBZ Datasheet(PDF) 11 Page - Analog Devices |
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AD6642EBZ Datasheet(HTML) 11 Page - Analog Devices |
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11 / 33 page  AD6642 Rev. A | Page 10 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND DNC DNC AGND AVDD CLK– CLK+ AVDD AGND VIN–B VIN+B AGND 1 234 5 6 78 9 10 11 12 AGND AGND DNC AGND AVDD AVDD AVDD AVDD AGND VCMB AGND AGND DNC AGND AGND CSB SDIO SCLK PDWN SYNC MODE AGND AGND VIN+A DNC DNC AGND AVDD AVDD AVDD AVDD AVDD AVDD AGND VCMA VIN–A AGND AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DNC DNC DNC DNC DNC DNC D0–AB D2–AB D4–AB D6–AB D8–AB D10–AB DNC K DNC DNC DNC DNC DNC D0+AB D2+AB D4+AB D6+AB D8+AB D10+AB DNC DNC DNC DNC DNC DNC D1–AB D3–AB D5–AB D7–AB D9–AB DCO–AB DNC A B C D E F G H J L M DNC DNC DNC DNC DNC D1+AB D3+AB D5+AB D7+AB D9+AB DCO+AB Figure 4. Pin Configuration (Top View) Table 9. Pin Function Descriptions Pin No. Mnemonic Type Description A5, A8, B5, B6, B7, B8, D4, D5, D6, D7, D8, D9, E2, E3, E4, E5, E6, E7, E8, E9, E10, E11 AVDD Supply Analog Power Supply (1.8 V Nominal) A1, A4, A9, A12, B1, B2, B4, B9, B11, B12, C2, C3, C10, C11, D3, D10, E1, E12, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12 AGND Ground Analog Ground H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal) G1, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12 DRGND Ground Digital Output Driver Ground A7 CLK+ Input ADC Clock Input—True A6 CLK− Input ADC Clock Input—Complement C12 VIN+A Input Differential Analog Input Pin (+) for Channel A D12 VIN−A Input Differential Analog Input Pin (−) for Channel A D11 VCMA Output Common-Mode Level Bias Output for Analog Input Channel A A11 VIN+B Input Differential Analog Input Pin (+) for Channel B A10 VIN−B Input Differential Analog Input Pin (−) for Channel B B10 VCMB Output Common-Mode Level Bias Output for Analog Input Channel B A2, A3, B3, C1, D1, D2, J1 to J6, K1 to K6, L1 to L6, M1 to M6 DNC Do Not Connect K7 D0+AB Output Channel A and Channel B LVDS Output Data 0—True J7 D0−AB Output Channel A and Channel B LVDS Output Data 0—Complement M7 D1+AB Output Channel A and Channel B LVDS Output Data 1—True L7 D1−AB Output Channel A and Channel B LVDS Output Data 1—Complement |
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