AD6642EBZ datasheet(12/33 Pages) AD

12 / 33 page

AD6642

Rev. A | Page 11 of 32

Pin No.

Mnemonic

Type

Description

D2+AB

Output

Channel A and Channel B LVDS Output Data 2—True

D2−AB

Output

Channel A and Channel B LVDS Output Data 2—Complement

D3+AB

Output

Channel A and Channel B LVDS Output Data 3—True

D3−AB

Output

Channel A and Channel B LVDS Output Data 3—Complement

D4+AB

Output

Channel A and Channel B LVDS Output Data 4—True

D4−AB

Output

Channel A and Channel B LVDS Output Data 4—Complement

D5+AB

Output

Channel A and Channel B LVDS Output Data 5—True

D5−AB

Output

Channel A and Channel B LVDS Output Data 5—Complement

K10

D6+AB

Output

Channel A and Channel B LVDS Output Data 6—True

J10

D6−AB

Output

Channel A and Channel B LVDS Output Data 6—Complement

M10

D7+AB

Output

Channel A and Channel B LVDS Output Data 7—True

L10

D7−AB

Output

Channel A and Channel B LVDS Output Data 7—Complement

K11

D8+AB

Output

Channel A and Channel B LVDS Output Data 8—True

J11

D8−AB

Output

Channel A and Channel B LVDS Output Data 8—Complement

M11

D9+AB

Output

Channel A and Channel B LVDS Output Data 9—True

L11

D9−AB

Output

Channel A and Channel B LVDS Output Data 9—Complement

K12

D10+AB

Output

Channel A and Channel B LVDS Output Data 10—True

J12

D10−AB

Output

Channel A and Channel B LVDS Output Data 10—Complement

M12

DCO+AB

Output

Data Clock LVDS Output for Channel A and Channel B—True

L12

DCO−AB

Output

Data Clock LVDS Output for Channel A and Channel B—Complement

MODE

Input

Mode Select Pin (Logic Low Enables NSR; Logic High Disables NSR)

SYNC

Input

Digital Synchronization Pin

PDWN

Input

Power-Down Input (Active High)

SCLK

Input

SPI Clock

SDIO

Input/Output

SPI Data

CSB

Input

SPI Chip Select (Active Low)

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