WM8768EDSSLASHR datasheet(15/38 Pages) WOLFSON

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Production Data

WM8768

PD Rev 4.1 March 2005

In hardware mode (MODE pin set high) the MUTE pin becomes a bi-directional pin. Therefore if it is

driven low the device will never softmute. If it is driven high then all channels will softmute

immediately.

However if the pin is connected to a high impedance, or left floating, then when all four internal zero

flags are raised. the WM8768 will also drive a weak logic high signal on the MUTE pin (output

impedance 10kOhms) which can be used to drive an external device.

It is not possible to perform analogue mute in Hardware mode.

Ω

Figure 10 MUTE Logic in Hardware Mode

INPUT FORMAT SELECTION

In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type

and input data word length for the DAC.

ML/I2S

MC/IWL

INPUT DATA MODE

24-bit right justified

20-bit right justified

16-bit I

24-bit I

Table 8 Input Format Selection

Note:

In 24 bit I

2S mode, any width of 24 bits or less is supported provided that the left/right clocks

(LRCLK) are high for a minimum of 24 bit clocks (BCLK) and low for a minimum of 24 bit clocks. If

exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a

16 bit data mode.

DE-EMPHASIS CONTROL

In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to

be applied.

MD/DM

DE-EMPHASIS

Off

Table 9 De-emphasis Control

WM8768EDS/R Datasheet(PDF) 15 Page - Wolfson Microelectronics plc