WM8768EDSSLASHR datasheet(21/38 Pages) WOLFSON

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Production Data

WM8768

PD Rev 4.1 March 2005

DAC OUTPUT CONTROL

The DAC output control word determines how the left and right inputs to the audio Interface are

applied to the left and right DACs:

BIT

LABEL

DEFAULT

DESCRIPTION

PL[3:0]

Left

Output

Right

Output

0000

Mute

0001

Left

Mute

0010

Right

Mute

0011

(L+R)/2

Mute

0100

Mute

Left

0101

Left

0110

Right

Left

0111

(L+R)/2

Left

1000

Mute

Right

1001

Left

Right

1010

Right

1011

(L+R)/2

Right

1100

Mute

(L+R)/2

1101

Left

(L+R)/2

1110

Right

(L+R)/2

0000010

DAC Control

8:5

PL[3:0]

1001

1111

(L+R)/2

DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits:

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

1:0

FMT

[1:0]

Interface format Select

00 : right justified mode

01: left justified mode

10: I

2S mode

11: DSP Modes A or B

In left justified, right justified or I

2S modes, the LRP register bit controls the polarity of LRCLK. If this

bit is set high, the expected polarity of LRCLK will be the opposite of that shown Figure 13, Figure 14

and Figure 15. Note that if this feature is used as a means of swapping the left and right channels, a

1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select

between modes A and B.

BIT

LABEL

DEFAULT

DESCRIPTION

In left/right/I

2S modes:

LRCLK Polarity (normal)

0 : normal LRCLK polarity

1: inverted LRCLK polarity

0000011

Interface Control

LRP

In DSP mode:

0 : DSP mode A

1: DSP mode B

WM8768EDS/R Datasheet(PDF) 21 Page - Wolfson Microelectronics plc

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