AD2S1210WDSTZ datasheet(25/37 Pages) AD

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AD2S1210

Rev. A | Page 24 of 36

DIGITAL INTERFACE

The angular position and angular velocity are represented by

binary data and can be extracted either via a 16-bit parallel

interface or via a 4-wire serial interface that operates at clock

rates of up to 25 MHz. The AD2S1210 programmable functions

are controlled using a set of on-chip registers. Data is written to

these registers using either the serial or the parallel interface.

SOE INPUT

The serial output enable pin, SOE, is held high to enable the

parallel interface. The SOE pin is held low to enable the serial

interface, which places Pin DB0 to Pin DB12 in the high imped-

ance state. Pin DB13 is the serial clock input (SCLK), Pin DB14

is the serial data input (SDI), Pin DB15 is the serial data output

(SDO), and WR/FSYNC is the frame synchronization input.

SAMPLE INPUT

The AD2S1210 operates on a Type II tracking closed-loop

principle. The loop continually tracks the position and velocity

of the resolver without the need for external conversion and

wait states. The position and velocity registers are external to

the loop and are updated with a high-to-low transition of the

SAMPLE signal. This pin must be held low for at least t16 ns

to guarantee correct latching of the data.

DATA FORMAT

The digital angle data represents the absolute position of the

resolver shaft as a 10-bit to 16-bit unsigned binary word. The

digital velocity data is a 10-bit to 16-bit twos complement word,

which represents the velocity of the resolver shaft rotating in

either a clockwise or a counterclockwise direction.

PARALLEL INTERFACE

The parallel interface is selected holding the SOE pin high. The

chip select pin, CS, must be held low to enable the interface.

Writing to the AD2S1210

The on-chip registers of the AD2S1210 are written to, in parallel

mode, using an 8-bit parallel interface, D7 to D0, and the WR/

FSYNC pin. The MSB of each 8-bit word written to the AD2S1210

indicates whether the 8-bit word is a register address or data.

The MSB (D7) of each register address defined on the AD2S1210

is high (see the

section). The MSB of each data

word written to the AD2S1210 is low. To write to one of the

registers, the user must first place the AD2S1210 into configura-

tion mode using the A0 and A1 inputs. Then the 8-bit address

should be written to the AD2S1210 using Pin DB7 to Pin DB0,

and latched using the rising edge of the

WR/FSYNC input. The

data can then be presented on Pin DB7 to Pin DB0 and again

latched into the part using the WR/FSYNC input.

shows

the timing specifications to follow when writng to the configura-

tion registers. Note that the

Figure 28

RD input should be held high when

writing to the AD2S1210.

Reading from the AD2S1210

The following data can be read back from the AD2S1210:

•

Angular position

•

Angular velocity

•

Fault register data

•

Status of on-chip registers

The angular position and angular velocity data can be read back

in either normal mode or configuration mode. To read the

status of the fault register or the remaining on-chip registers,

the part must be put into configuration mode.

Reading from the AD2S1210 in Configuration Mode

To read back data stored in one of the on-chip registers, including

the fault register, the user must first place the AD2S1210 into

configuration mode using the A0 and A1 inputs. The 8-bit address

of the register to be read should then be written to the part, as

described in the Writing to the AD2S1210 section. This transfers

the relevant data to the output register. The data can then be

read using the RD input as described previously. When reading

back data from any of the read/write registers (see

), the

8-bit word consists of the seven bits of data in the relevant register,

D6 to D0, and an error bit, D7. If the error bit is returned high,

this indicates that the data read back from the device does not

match the configuration data written to the device in the previous

write cycle.

Table 10

If the user wants to read back the angular position or velocity

data while in configuration mode, a falling edge of the SAMPLE

input is required to update the information in the position and

velocity registers. The data in these registers can then be read back

by addressing the required register and reading back the data as

described previously.

shows the timing specifications to

follow when reading from the configuration registers.

Figure 29

Reading from the AD2S1210 in Normal Mode

To read back position or velocity data from the AD2S1210, the

information stored in the position and velocity registers should

first be updated using the SAMPLE input. A high-to-low transition

on the SAMPLE input transfers the data from the position and

velocity integrators to the position and velocity registers. The

fault register is also updated on the high-to-low transition of the

SAMPLE input. The status of the A0 and A1 inputs determines

whether the position or velocity data is transferred to the output

data to the output register. Finally, the RD input is used to read

the data from the output register and to enable the output buffer.

The output buffer is enabled when CS and RD are held low. The

data pins return to a high impedance state when RD returns to

a high state. If the user is reading data continuously, RD can be

reapplied a minimum of t20 ns after it was released.

The timing requirements for the read cycle are shown in Figure 30.

Note that the WR/FSYNC input should be high when RD is low.

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