AD2S1210WDSTZ datasheet(26/37 Pages) AD

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AD2S1210

Rev. A | Page 25 of 36

Clearing the Fault Register

The LOT pin and/or the DOS pin of the AD2S1210 are taken

low to indicate that a fault has been detected. The AD2S1210 is

capable of detecting eight separate fault conditions. To determine

which condition triggered the fault indication, the user is required

to enter configuration mode and read the fault register. To reset

the fault indicators, an additional SAMPLE pulse is required.

This ensures that any faults that may occur between the initial

sampling and subsequent reading of the fault register are captured.

Therefore, to read and clear the fault register, the following

sequence of events is required:

A high-to-low transition of the SAMPLE input.

The SAMPLE input should be held low for t16 ns and then

can be returned high.

The AD2S1210 should be put into configuration mode,

that is, A0 and A1 are both set to logic high.

The fault register should be read as described in the

Reading from the AD2S1210 in Configuration Mode

section.

A second high-to-low transition of the SAMPLE input

clears the fault indications on the DOS and/or LOT pins.

Note that in the event of a persistent fault, the fault indica-

tors are reasserted within the specified fault time latency.

Figure 31 shows the timing specifications to follow when

clearing the fault register.

Note that the last valid register address written to the AD2S1210

prior to exiting configuration mode is again valid when reentering

configuration mode. It is therefore recommended that when

initial configuration of the AD2S1210 is complete, the fault address

should be written to the AD2S1210 before leaving configuration

mode. This simplifies the reading and clearing of the fault register

in normal operation because it is now possible to access the

position, velocity, and fault information by toggling the A0 and

A1 pins without requiring additional register addressing.

fCLKIN

CLKIN

A0, A1

DB0 TO DB7

ADDRESS

DATA

NOTES

2. RD SHOULD BE HELD HIGH WHEN WRITING TO THE AD2S1210.

DON’T CARE.

Figure 28. Parallel Port Write Timing—Configuration Mode

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