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PIC16F74-E/SS Datasheet(PDF) 78 Page - Microchip Technology |
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PIC16F74-E/SS Datasheet(HTML) 78 Page - Microchip Technology |
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78 / 174 page  PIC16F7X DS30325B-page 76 2002 Microchip Technology Inc. FIGURE 10-5: ASYNCHRONOUS RECEPTION Steps to follow when setting up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, then set enable bit RCIE. 4. If 9-bit reception is desired, then set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE in the INTCON register are set. TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION START bit bit7/8 bit1 bit0 bit7/8 bit0 STOP bit START bit START bit bit7/8 STOP bit RX (pin) Reg Rcv Buffer Reg Rcv Shift Read Rcv Buffer reg RCREG RCIF (Interrupt Flag) OERR bit CREN Word 1 RCREG Word 2 RCREG STOP bit Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS 0Bh, 8Bh, 10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear. |
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