LP6283–00

Version 0.0

Jul.-2016

Email: marketing@lowpowersemi.com

www.lowpowersemi.com

Page 4 of 10

Preliminary Datasheet

LP6283

Functional Pin Description

Pin Num

Pin Name

Description

1

LDO_I

Linear Regulator Power Source. Bypass LDO_I to GND a capacitor.

2

OPS

OPA Power Source. Bypass OPS to OGND a capacitor.

3

OGND

Ground for OPA. Connect this pin to ground.

4

OPP

OPA Non-Inverting Input.

5

OPN

OPA Inverting Input.

6

OPO

OPA Output.

7

XAO

Reset Function Output. Open drain.

8

GVOFF

High-Voltage Switch Control Input. When GVOFF is high the high voltage switch between VGH and VGHM

is on and the high-voltage switch between VGHM and DRN is off. W hen GVOFF is low, the switch

between VGH and VGHM is off and the switch between VGHM and DRN is on.

9

EN

Enable Input. Pulling EN high, turn on boost regulator and VGH charge pump.

10

FB2

Buck Regulator Feedback Input. Connect to an external resistive voltage divider from the output to

FB2 to set the output voltage.

11

OUT

Buck Regulator Output Sense. Connect OUT pin to the Buck regulator output.

12

NC

No Connection.

13, 14

LX2

Buck Regulator Switching Node. LX2 is the source of the internal NMOS. Connect the inductor and

schottky diode to LX2.

15

BST

Buck Regulator Bootstrap Pin. BST is the supply for the high-side MOSFET gate driver. Connect a 0.1

μF

ceramic capacitor from BST to LX2.

16, 17

IN2

Buck Regulator Supply Input. Bypass IN2 to PGND a capacitor.

18

GND

Analog GND.

19

VDET

Voltage Detector Input. Connect to an external resistive voltage divider from the VIN to AGND.

20

INVL

Internal Regulator and Startup Circuitry Supply Input. The input voltage range of INVL is between +8V to

+14V. Connect a ceramic capacitor between INVL and GND.

21

VREG

Internal Regulator Output. Bypass VREG to GND a capacitor.

22

FSEL

Frequency Select Pin. Set FSEL to high for 750kHz operation. Set this pin to low for 500kHz operation.

23

CLIM

Boost Regulator OCP level setting by an external resistor to GND.

24

SS

Soft-Start Control Pin. Connect a soft-start capacitor to this pin. If external capacitor is less than 220pF,

soft-start is controlled internally and soft-start time is 10ms.

25, 26

LX1

Boost Regulator Switching Node. Connect the inductor and the schottky diode to LX1.

27, 28

PGND

Power Ground.

29

GD_I

Boost Regulator Output Sense Pin. Connected this pin to the boost regulator output.

30

GD

External PMOS Gate Drive Pin. GD pin will be pulled low when EN is high.

31

FB1

Boost Regulator Feedback Input. Connect to an external resistive voltage divider from the output to

FB1 to set the output voltage.

32

COMP

Boost Regulator Error Amplifier Compensation Pin.

33

THR

VGHM Falling Regulation Adjustment Input. Connect to an external resistive voltage divider from the

supply to GND to adjust the VGHM falling regulation set point.

34

SUPP

VGH Charge-Pump Regulator Power Source. Bypass SUPP to CPGND a ceramic capacitor.

35

CPGND

Power Ground for Charge Pump.

36

DRVP

VGH Charge-Pump Regulator Driver Output.

37

DLY

GPM Delay Input. Connect a capacitor between DLY and GND.

38

FBP

VGH Charge-Pump Regulator Feedback Input. Connect to an external resistive voltage divider from

the VGH to GND to set the output voltage.

39

VGH

GPM Input.

40

VGHM

GPM Output.