8.2.3 Application Curve

IOL (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

D001

VCC 5.5V

Figure 8-2. VOL vs IOL

8.3 Power Supply Recommendations

The power supply may be any voltage between the MIN and MAX supply voltage rating located in the Section

5.3.

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is

recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01-µF or 0.022-µF

capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to

reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies

of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.

8.4 Layout

8.4.1 Layout Guidelines

Inputs should not float when using multiple bit logic devices. In many cases, functions or parts of functions of

digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND

gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected

because the undefined voltages at the outside connections result in undefined operational states.

Specified in the Figure 8-3 are rules that must be observed under all circumstances. All unused inputs of digital

logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should

be applied to any particular unused input depends on the function of the device. Generally, they will be tied to

GND or VCC, whichever makes more sense or is more convenient.

8.4.2 Layout Example

VCC

Unused Input

Input

Output

Output

Input

Unused Input

Figure 8-3. Layout Example

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SN54ACT244, SN74ACT244

SCAS517G – JUNE 1995 – REVISED MARCH 2024

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