ADATE320KCPZ datasheet(51/83 Pages) AD

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ADATE320

Data Sheet

Rev. B | Page 50 of 82

THEORY OF OPERATION

SERIAL PROGRAMMABLE INTERFACE (SPI)

SPI Hardware Interconnect Details

ADATE320

(CHIP n)

SCLK

SDI

SDO

BUSY

ADATE320

(CHIP 1)

SCLK

SDI

SDO

BUSY

ADATE320

(CHIP 0)

SCLK

SDI

SDO

BUSY

SCLK

CS[n:0]

SDI

SDO

BUSY

Figure 127. Multiple SPI with a Shared SDO Line

SPI Reset Sequence and the RST Pin

The internal state of the ADATE320 is indeterminate following

power-up. For this reason, it is necessary to perform a valid

hardware reset sequence as soon as the power supplies are

stabilized. The ADATE320 provides an active low reset pin

(RST) for this purpose. Asserting RST asynchronously initiates

a reset sequence. Furthermore, the RST pin must be asserted

before and during the power-up cycling sequence, and released

only after all power supplies are guaranteed to be stable.

A soft reset sequence can also be initiated under SPI software

control by writing to the SPI_RESET bit (see Figure 147). In the

case of a soft reset, the sequence begins on the first rising edge

of SCLK following the release of CS, subject to the normal setup

and hold times. Certain actions occur immediately upon the

initiation of the reset request, whereas other actions require

several cycles of SCLK.

The following asynchronous actions occur immediately following

the detection of the reset request, whether it was hardware (RST) or

software (SPI) initiated:

•

Assert open-drain BUSY pin

•

Force all control registers to their default reset states as

defined in Table 29

•

Clear all calibration registers to their default reset states as

defined in Table 29

•

Override all DAC analog outputs and force dc levels to

VDUTGND, disable the driver and PPMU functions

•

Enable active loads with IOHx = IOLx = 100 µA

(uncalibrated and expected to vary with offset from device

to device); soft connect DUTx pins to VCOM = VDUTGND

The device remains in this static reset state indefinitely until the

clocked portion of the sequence begins with either the first rising

edge of SCLK following the release of RST in the case of an

asynchronous hardware reset, or the second rising edge of

SCLK following the release of CS in the case of a software SPI

reset. Regardless of how the reset sequence was initiated, the

clocked portion of the sequence requires 744 SCLK cycles to

run through to completion, and the open-drain BUSY pin (if

available) remains asserted until all clock cycles are received.

The following actions occur during the clocked portion of the

reset sequence:

•

Complete initialization of internal SPI controller

•

Write default values to appropriate DAC X2 registers

•

Enable the thermal alarm with a 100°C threshold

•

Disable the PPMU clamp and overvoltage detect (OVD)

alarms

The 744 rising edges of SCLK release BUSY and start a self

timed DAC deglitch period of approximately 3 µs. DAC voltages

begin to change as soon as the deglitch circuits time out. An

additional 10 µs is required to settle to the final values. A full

reset sequence thus requires approximately 30 µs, comprising 16 µs

(744 cycles × 20 ns) for post reset initialization, 3 µs for DAC

deglitch, and another 10 µs for DAC analog level settling.

ADATE320KCPZ Datasheet(PDF) 51 Page - Analog Devices

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