ADATE320KCPZ datasheet(17/83 Pages) AD

17 / 83 page

ADATE320

Data Sheet

Rev. B | Page 16 of 82

Parameter

Min

Typ

Max

Unit

Test

Level

Test Conditions/Comments

PPMU_Mx Pin, Parasitic Output

Capacitance

Parasitic capacitance contributed by pin

PPMU_Mx Pin, External Load

Capacitance

100

External capacitance tolerated by pin

(exceeding this value may cause instability)

PPMU VOLTAGE CLAMPS (FI)

PPMU enabled in FIMI, PPMU clamps

enabled; clamp accuracy applies only

when |PCHx − PCLx| ≥ 1.0 V

Low Voltage Clamp Range (PCLx)

−1.5

+3.5

High Voltage Clamp Range (PCHx)

−0.5

+4.5

Offset, Voltage Clamps (PCHx/PCLx)

−300

+300

Range B, PPMU force ±0.5 mA into open;

PCHx measured at DAC Code 0x4000 (0.0 V)

with PCLx at DAC Code 0x0000 (−2.5 V); PCLx

measured at DAC Code 0x4000 (0.0 V) with

PCHx at DAC Code 0xFFFF (+7.5 V)

OffsetTC,Voltage Clamps (PCHx/PCLx)

±0.5

mV/°C

Gain, Voltage Clamps (PCHx/PCLx)

1.0

1.1

V/V

Range B, PPMU force ±0.5 mA into open; PCHx

gain derived from measurements at DAC

Code 0x4000 (0.0 V) and DAC Code 0x8CCC

(3.0 V) with PCLx at DAC Code 0x0000

(−2.5 V); PCLx gain derived from measure-

ments at DAC Code 0x4000 (0.0 V) and

DAC Code 0x8CCC (3.0 V) with PCHx at

DAC Code 0xFFFF (7.5 V)

Gain TC, Voltage Clamps (PCHx/PCLx)

±25

ppm/°C

INL, Voltage Clamps (PCHx/PCLx)

−20

+20

Range B, PPMU force ±0.5 mA into open

after two-point gain/offset calibration;

measured over PPMU clamp functional

range

Positive Voltage Clamp, Voltage

Droop (Source)

−50

+50

∆V at DUTx pin, Range A, PCHx = +4.0 V,

PCLx = −1.0 V, PPMU force 5.0 mA and

40 mA into open circuit, calibrated

Negative Voltage Clamp, Voltage

Droop (Sink)

−50

+50

∆V at DUTx pin, Range A, PCHx = +4.0 V,

PCLx = −1.0 V, PPMU force −5.0 mA and

−40 mA into open circuit, calibrated

DUTGND Voltage Accuracy

−5

±1

Over ±0.1 V range; measured at end points

of clamp functional range

PPMU CURRENT CLAMPS (FV)

PPMU enabled in FVMV, dc accuracy of the

current clamps only applies over the

following conditions: 30% FS ≤ PCHx ≤

100% FS or −100% FS ≤ PCLx ≤ −30% FS

Functional Range

Low Current Clamp (PCLx)

−120

−20

%FS

For example, −120% FS in Range A is

−48 mA and −20% FS in Range A is −8 mA

High Current Clamp (PCHx)

120

%FS

For example, 20% FS in Range A is 8 mA

and 120% FS in Range A is 48 mA

DC Accuracy Range

Low Current Clamp (PCLx)

−100

−30

%FS

For example, −100% FS in Range A is

−40 mA and −30% FS in Range A is −12 mA

High Current Clamp (PCHx)

100

%FS

For example, 30% FS in Range A is 12 mA

and 100% FS in Range A is 40 mA

Static Current Limit, Source and

Sink, All Ranges

±120

±140

±160

%FS

PCLx at DAC Code 0x0000 (−2.5 V), PCHx

at DAC Code 0xFFFF (7.5 V), sink: force

−1.5 V, short DUTx to 4.5 V, source: force

4.5 V, short DUTX to −1.5 V

Offset, Current Clamps (PCHx/PCLx)

−10

+10

%FSR

All ranges; PPMU force ±1.0 V into 0.0 V1

Offset TC, Current Clamps

(PCHx/PCLx)

±0.02

%FSR/°C

All ranges

ADATE320KCPZ Datasheet(PDF) 17 Page - Analog Devices

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