PCI7510 datasheet(6/234 Pages) TI

6 / 234 page

5.4

ExCA Interrupt and General Control Register

5–8

. . . . . . . . . . . . . . . . . . .

5.5

ExCA Card Status-Change Register

5–9

. . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6

ExCA Card Status-Change Interrupt Configuration Register

5–10

. . . . . . .

5.7

ExCA Address Window Enable Register

5–11

. . . . . . . . . . . . . . . . . . . . . . . .

5.8

ExCA I/O Window Control Register

5–12

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9

ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers

5–13

. . . .

5.10

ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers

5–13

. . . .

5.11

ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers

5–14

. . . . .

5.12

ExCA I/O Windows 0 and 1 End-Address High-Byte Registers

5–14

. . . .

5.13

ExCA Memory Windows 0–4 Start-Address Low-Byte Registers

5–15

. . .

5.14

ExCA Memory Windows 0–4 Start-Address High-Byte Registers

5–16

. . .

5.15

ExCA Memory Windows 0–4 End-Address Low-Byte Registers

5–17

. . . .

5.16

ExCA Memory Windows 0–4 End-Address High-Byte Registers

5–18

. . .

5.17

ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers

5–19

. .

5.18

ExCA Memory Windows 0–4 Offset-Address High-Byte Registers

5–20

5.19

ExCA Card Detect and General Control Register

5–21

. . . . . . . . . . . . . . . .

5.20

ExCA Global Control Register

5–22

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.21

ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers

5–23

. . .

5.22

ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers

5–23

. . .

5.23

ExCA Memory Windows 0–4 Page Registers

5–24

. . . . . . . . . . . . . . . . . . .

CardBus Socket Registers (Functions 0 and 1)

6–1

. . . . . . . . . . . . . . . . . . . . . .

6.1

Socket Event Register

6–2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2

Socket Mask Register

6–3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3

Socket Present State Register

6–4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4

Socket Force Event Register

6–5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5

Socket Control Register

6–7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6

Socket Power Management Register

6–8

. . . . . . . . . . . . . . . . . . . . . . . . . . .

OHCI Controller Programming Model

7–1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1

Vendor ID Register

7–2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2

Device ID Register

7–2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3

Command Register

7–3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4

Status Register

7–4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5

Class Code and Revision ID Register

7–5

. . . . . . . . . . . . . . . . . . . . . . . . . .

7.6

Latency Timer and Class Cache Line Size Register

7–5

. . . . . . . . . . . . . .

7.7

Header Type and BIST Register

7–6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8

OHCI Base Address Register

7–6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9

TI Extension Base Address Register

7–7

. . . . . . . . . . . . . . . . . . . . . . . . . . .

7.10

CardBus CIS Base Address Register

7–8

. . . . . . . . . . . . . . . . . . . . . . . . . . .

7.11

CardBus CIS Pointer Register

7–8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.12

Subsystem Identification Register

7–9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.13

Power Management Capabilities Pointer Register

7–9

. . . . . . . . . . . . . . .

7.14

Interrupt Line Register

7–10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.15

Interrupt Pin Register

7–10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.16

Minimum Grant and Maximum Latency Register

7–11

. . . . . . . . . . . . . . . . .

PCI7510 Datasheet(PDF) 6 Page - Texas Instruments

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