PCI7510 datasheet(30/234 Pages) TI

30 / 234 page

2–11

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The

terminal numbers are also listed for convenient reference.

Table 2–5. Power Supply Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

I/O

DESCRIPTION

GND

6, 24, 39, 62,

114, 128, 143,

162, 180, 195

E01, K01, N01,

W06, P19, K19,

G19, A15, A10,

A07

–

Device ground terminal

VCC

14, 34, 47, 70,

123, 138, 151,

170, 190, 203

G01, M01, R01,

W08, L19, H19,

E19, A13, A08,

A05

–

Power supply terminal for I/O and internal voltage regulator

VCCCB

146, 175

G14, A11

–

Clamp voltage for PC CardBus interface. Matches card B signaling environment,

5 V or 3.3 V

VCCP

29, 58

L01, W05

–

Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V

VR_EN

H05

Internal voltage regulator enable. Active low

VR_PORT

13, 124

G02, L18

I/O

1.8 V output from voltage regulator

Table 2–6. PC Card Power Switch Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

I/O

DESCRIPTION

VD1/VCCD0

VD0/VCCD1

VD3/VPPD0

VD2/VPPD1

206

205

208

207

E06

B05

A04

C05

Logic controls to the TPS2211A or TPS2221 PC Card power interface

Table 2–7. PCI System Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

I/O

DESCRIPTION

GRST

H02

Global reset. When the global reset is asserted, the GRST signal causes the PCI7510 device to place all

output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device

is completely in its default state. GRST must be connected to POWER_OK.

PCLK

H01

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the

rising edge of PCLK.

PRST

H03

PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI7510 device to place all output

buffers in a high-impedance state and reset internal registers. When PRST is asserted, the device is

completely nonfunctional. After PRST is deasserted, the PCI7510 device is in a default state.

When SUSPEND and PRST are asserted, the device is protected from PRST clearing the internal registers.

All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

PCI7510 Datasheet(PDF) 30 Page - Texas Instruments

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