ADAS1000BCPZ datasheet(78/80 Pages) AD

78 / 80 page

ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

POWER SUPPLY, GROUNDING, AND DECOUPLING

STRATEGY

The ADAS1000/ADAS1000-1/ADAS1000-2 must have ample

supply decoupling of 0.01 μF on each supply pin located as close

to the device pin as possible, ideally right up against the device.

In addition, there must be one 4.7 μF capacitor for each of the

power domains, AVDD and IOVDD, again located as close to

the device as possible. IOVDD is best split from AVDD due to

its noisy nature.

Similarly, the ADCVDD and DVDD power domains each

require one 2.2 μF capacitor with ESR in the range of 0.5 Ω to

2 Ω. The ideal location for each 2.2 μF capacitor is dependent

on package type. For the LQFP package and DVDD decoupling,

the 2.2 μF capacitor is best placed between Pin 30 and Pin 31,

while for ADCVDD, place the 2.2 μF capacitor between Pin 55

and Pin 56. Similarly for the LFCSP package, the DVDD 2.2 μF

capacitor is ideal between Pin 43 and Pin 44, and between Pin 22

and Pin 23 for ADCVDD. A 0.01 μF capacitor is recommended

for high frequency decoupling at each pin. The 0.01 μF capacitors

must have low effective series resistance (ESR) and effective series

inductance (ESL), such as the common ceramic capacitors that

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching.

Avoid digital lines running under the device because these

couple noise onto the device. Allow the analog ground plane to

run under the device to avoid noise coupling. The power supply

lines must use as large a trace as possible to provide low impedance

paths and reduce the effects of glitches on the power supply

line. Shield fast switching digital signals with digital ground to

avoid radiating noise to other parts of the board and never run

them near the reference inputs. It is essential to minimize noise

on VREF lines. Avoid crossover of digital and analog signals.

Traces on opposite sides of the board must run at right angles to

each other. This reduces the effects of feedthrough throughout

the board. As is the case for all thin packages, take care to avoid

flexing the package and to avoid a point load on the surface of

this package during the assembly process.

During layout of board, ensure that bypass capacitors are placed

as close to the relevant pin as possible, with short, wide traces

ideally on the topside.

AVDD

While the ADAS1000/ADAS1000-1/ADAS1000-2 are

designed to operate from a wide supply rail, 3.15 V to 5.5 V,

the performance is similar over the full range, but overall

power increases with increasing voltage.

ADCVDD AND DVDD SUPPLIES

The AVDD supply rail powers the analog blocks in addition to

the internal 1.8 V regulators for the ADC and the digital core.

If using the internal regulators, connect the VREG_EN pin to

AVDD and then use the ADCVDD and DVDD pins for

decoupling purposes.

The DVDD regulator can be used to drive other external digital

circuitry as required; however the ADCVDD pin is purely

provided for bypassing purposes and does not have available

current for other components.

Where overall power consumption must be minimized, using

external 1.8 V supply rails for both ADCVDD and DVDD

would provide a more efficient solution. The ADCVDD and

DVDD inputs have been designed to be driven externally and

the internal regulators can be disabled by tying VREG_EN pin

directly to ground.

UNUSED PINS/PATHS

In applications where not all ECG paths or functions might be

used, the preferred method of biasing the different functions is

as follows:

•

Unused ECG paths power up disabled. For low power

operation, keep them disabled throughout operation.

Ideally, connect these pins to RLD_OUT if not being used.

•

Unused external respiration inputs can be tied to ground if

not in use.

•

If unused, the shield driver can be disabled and output left

to float.

•

CM_OUT, CAL_DAC_IO, DRDY, GPIOx, CLK_IO,

SYNC_GANG can be left open.

LAYOUT RECOMMENDATIONS

To maximize CMRR performance, pay careful attention to

the ECG path layout for each channel. All channels must be

identical to minimize difference in capacitance across the paths.

Place all decoupling as close to the ADAS1000/ADAS1000-1/

ADAS1000-2 devices as possible, with an emphasis on ensuring

that the VREF decoupling be prioritized, with VREF decoupling

on the same side as the ADAS1000/ADAS1000-1/ADAS1000-2

devices, where possible.

Rev. B | Page 78 of 80

ADAS1000BCPZ Datasheet(PDF) 78 Page - Analog Devices

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