AD9671EBZ datasheet(30/61 Pages) AD

30 / 61 page

Data Sheet

AD9671

Rev. A| Page 29 of 60

drive the STBY pin from a 3.3 V logic level, insert a 1 kΩ

resistor in series with this pin to limit the current.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on VREF are discharged

when entering power-down mode and must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in power-down mode: shorter cycles

result in proportionally shorter wake-up times. To restore the

device to full operation, approximately 375 μs is required when

using the recommended 1 μF and 0.1 μF decoupling capacitors

on the VREF pin and the 0.01 μF decoupling capacitors on the

GAIN± pins. Most of this time is dependent on gain decoupling;

higher value decoupling capacitors on the GAIN± pins result in

longer wake-up times.

A number of other power-down options are available when using

the SPI port interface. The user can individually power down

each channel or place the entire device into standby mode. When

fast wake-up times are required, standby mode allows the user

to keep the internal PLL powered up. The wake-up time is slightly

dependent on gain. To achieve a 2 μs wake-up time when the

device is in standby mode, apply 0.8 V to the GAIN± pins.

Power and Ground Connection Recommendations

When connecting power to the AD9671, use two separate 1.8 V

supplies: one for analog (AVDD1) and one for digital (DRVDD).

If only one 1.8 V supply is available, route it to the AVDD1 pin

first and then tap it off and isolate it with a ferrite bead or a

filter choke preceded by decoupling capacitors for the DRVDD

pin.

If the user does not use the digital demodulator/decimator

functions for post ADC processing, the DVDD pin can be tied

to the 1.8 V DRVDD supply. When this is done, route the DVDD

supply first, tap it off, and isolate it with a ferrite bead or filter

choke preceded by decoupling capacitors for the DRVDD pin. It

is not recommended to use the same supply for AVDD1, DVDD,

and DRVDD.

For both high and low frequencies, use several decoupling

capacitors on all supplies. Place these capacitors near the point

of entry at the PCB level and near the device, with minimal trace

lengths.

When using the AD9671, a single PCB ground plane is sufficient.

With proper decoupling and smart partitioning of the analog,

digital, and clock sections of the PCB, optimum performance

can be easily achieved.

Advanced Power Control

For an ultrasound system, not all channels are needed during all

scanning periods. The POWER_START and POWER_STOP

values in the vector profile can be used to delay the channel

startup and turn the channel off after a certain number of samples.

These counters are relative to TX_TRIG±. The analog circuitry

needs to power up before the digital one and the advance time

(POWER_SETUP) for powering up the analog circuitry, before

POWER_START, is set up in Address 0x112 (see Table 33).

TX_TRIG±

POWER_STOP

(PROFILE SPECIFIC)

POWER_START

(PROFILE SPECIFIC)

POWER_SETUP

(SPI SET)

DIGITAL

POWER

ANALOG

POWER

Figure 44. Power Sequencing

DIGITAL OUTPUTS AND TIMING

JESD204B Transmit Top Level Description

The AD9671 digital output complies with the JEDEC Standard

JESD204B, Serial Interface for Data Converters. JESD204B is a

protocol to link the AD9671 to a digital processing device over

a serial interface up to 5 Gbps link speeds. The benefits of the

JESD204B interface include a reduction in required board area

for data interface routing, and enables smaller packages for

converter and logic devices. The AD9671 supports single, dual,

or quad lane interfaces.

JESD204B Overview

The JESD204B data transmit block, as shown in Figure 45,

assembles the parallel channel data from the ADC or digital

processing block into frames and uses 8B/10B encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of special

characters during the initial establishment of the link, and

additional synchronization is embedded in the data stream

thereafter. A matching external receiver is required to lock onto

the serial data stream and recover the data and clock. For

additional details on the JESD204B interface, users are

encouraged to refer to the JESD204B standard.

The AD9671 JESD204B transmit block maps the eight channel

outputs over a link. A link can be configured to use either

single, dual, or quad serial differential outputs, which are called

lanes. The JESD204B specification refers to a number of

parameters to define the link, and these parameters must match

between the JESD204B transmitter (AD9671 output) and

receiver.

The JESD204B link is described according to the parameters

listed in Table 14.

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