AD9670EBZ datasheet(34/48 Pages) AD

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Data Sheet

AD9674

Rev. A | Page 33 of 47

DIGITAL RF DECIMATOR

The AD9674 contains digital processing capability. Each channel

has two stages of processing available: RF decimator and HPF.

For test purposes, the input to the decimator can be a test

waveform. Normally, the input to the decimator is the output of

the ADC. The output of the decimator and filter is sent to the

serializer for output formatting.

The maximum data rate of the serializer is 1000 MSPS. Therefore,

if the sample rate of the ADC is greater than 65 MSPS, the RF

decimator (fixed rate of 2) must be enabled. The ADC resolution

is 14 bits. Saturation of the ADC is determined after the dc offset

calibration to ensure maximum dynamic range.

VECTOR PROFILE

To minimize the time needed to reconfigure device settings

while operating, the device supports configuration profiles. Up

to 32 profiles can be stored in the device. A profile is selected by a

5-bit index. A profile consists of a 64-bit vector, as described in

Table 21. Each parameter is concatenated to form the 64-bit profile

vector. The profile memory starts at Address 0xF00 and ends at

Address 0xFFF. The memory can be written in either stream

mode or address selected data mode. However, the memory

must be read using stream mode.

When writing or reading in stream mode while the SPI

configuration is set to MSB first mode (default setting for

reading the first profile that spans the address space between

0xF00 and 0xF07, and the SPI port is configured as MSB first,

the referenced address must be 0xF07 to allow reading from or

writing to the 64-bit profile in MSB mode. For more information

about stream mode, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

A buffer in the device stores the current profile data. When the

profile index is written in Register 0x10C, the selected profile is

read from memory and stored in the current profile buffer. The

profile memory is read/written in the SPI clock domain. After

the SPI writes the profile index value, it takes four SPI clock cycles

to read the profile from RAM and store it in the current profile

buffer. If the SPI is in LSB mode, these additional SPI clock cycles

are provided when the profile index register is written. If the SPI is

in MSB mode, an additional byte needs to be read or written to

update the profile buffer.

Updating the profile memory does not affect the data in the profile

buffer. The profile index register must be written to cause a refresh

of the current profile data, even if the profile index register is

written with the same value.

ADC OUTPUT OR

TEST WAVEFORM

DC OFFSET

CALIBRATION

RF DECIMATOR

MULTIBAND AAF

DECIMATE BY 2

FRAMER

SERIALIZER

HIGH-PASS

FILTER

Figure 49. Simplified Block Diagram of a Single Channel of RF Decimator

Table 21. Profile Definition

Field

Bits

Description

Reserved

HPF bypass

Digital HPF bypass

0 = disable (filter enabled)

1 = enable (filter bypassed)

POWER_START

ADC clock cycles counted from TX_TRIG± when the active channels are powered up

0x0000 = 0 clock cycles

0x0001 = 1 clock cycle

…

0x7FFF = 32,767 clock cycles

Reserved

POWER_STOP

ADC clock cycles counted from TX_TRIG± when the active channels are powered down

0x0000 = 0 clock cycles

0x0001 = 1 clock cycle

…

0x7FFF = Continuous run mode

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