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AD9675KBCZ Datasheet(PDF) 34 Page - Analog Devices |
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AD9675KBCZ Datasheet(HTML) 34 Page - Analog Devices |
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34 / 61 page  Data Sheet AD9675 Rev. A | Page 33 of 60 Set Additional Digital Output Configuration Options The JESD204B outputs are configured by default to produce a peak differential voltage of 262 mV, which satisfies the JESD204B specification for a transmit eye mask for an LV-OIF-11G-SR- based operation target of between 180 mV and 385 mV peak differential voltage, but other peak differential voltages can be accommodated. Address 0x015, Bits[6:4] settings allow output peak voltages. Additional options include the following: Invert polarity of the serial output data: Address 0x014, Bit 2 Flip (mirror) 10-bit word before output: Address 0x143, Bit 0 Channel data format (offset binary, twos complement, Gray code): Address 0x014, Bits[1:0] Options for interpreting the signal on the SYNCINB± pin: Address 0x156, Bit 5 Reenable Lanes After Configuration After modifying the JESD204B link parameters, enable the link, and then the synchronization process can begin. Enable the link by writing a Logic 0 to Address 0x142, Bit 0. Figure 46. AD9675 Digital Processing of JESD204B Lanes Table 19. AD9675 JESD204B Frame Alignment Monitoring and Correction Replacement Characters Scrambling Lane Synchronization Character to be Replaced Last Octet in Multiframe Replacement Character Off On Last octet in frame repeated from previous frame No K28.7 Off On Last octet in frame repeated from previous frame Yes K28.3 Off Off Last octet in frame repeated from previous frame Not applicable K28.7 On On Last octet in frame equals D28.7 No K28.7 On On Last octet in frame equals D28.3 Yes K28.3 On Off Last octet in frame equals D28.7 Not applicable K28.7 8-BIT/10-BIT ENCODER/ CHARACTER REPLACMENT SERIALIZER t . . . SYNCINB SYSREF SERDOUTx± A PATH ADC TEST PATTERN 16-BIT JESD204B TEST PATTERN 8-BIT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 T0 T1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 E0 E1 E2 E3 E4 E5 E6 E7 E10 E11 E12 E13 E14 E15 E16 E17 E8 E9 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E18 E19 E19 OPTIONAL SCRAMBLER 1 + x14 + x15 JESD204B TEST PATTERN 10-BIT TX_TRIG CHANNEL |
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