AD9675KBCZ datasheet(42/61 Pages) AD

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Data Sheet

AD9675

Rev. A | Page 41 of 60

RF DECIMATOR

The input to the RF decimator is either the ADC output data or

a test waveform, as described in the Digital Test Waveforms

section. The test waveforms are enabled per channel using

Address 0x11A (see Table 31).

DC Offset Calibration

The user can reduce dc offset through a manual system

calibration process. Measure the dc offset of every channel in

the system and then set a calibration value using Address 0x110

and Address 0x111. Note that these registers are both chip and

local addresses, meaning that they are accessed using the chip

address and device index. Bypass the dc offset calibration using

Address 0x10F, Bits[2:0].

Multiband AAF and Decimate by 2

The multiband filter is an FIR filter. It is programmable with low or

high bandwidth filtering. The filter requires 11 input samples to

populate the filter. The decimation rate is fixed at 2×. Therefore,

the decimation frequency is fDEC = fSAMPLE/2. Figure 57 and

Figure 58 show the frequency response of the filter, depending

on the mode. Figure 57 shows the attenuation amplitude over

the Nyquist frequency range. Figure 58 shows the pass band

response as nearly flat.

Figure 57. AAF Frequency Response (Frequency Scale Assumes

fADC = 2 × fDEC = 40 MHz)

Figure 58. AAF Frequency Response, Zoomed In (Frequency Scale Assumes

fADC = 2 × fDEC = 40 MHz)

High-Pass Filter

The user can apply a second-order Butterworth high-pass IIR

filter after the RF decimator. The filter has a cutoff of 700 kHz

for an encode clock of 50 MHz. The filter has a settling time of

2.5 μs. Therefore, if the ADC clock is 50 MHz, ignore the first

125 samples (2.5 μs/0.02 μs). Bypass or enable the filter in the

vector profile if the filter is enabled in Register 0x113, Bit 5. If

the filter is bypassed by setting Register 0x113, Bit 5 to 1, the

filter cannot be enabled from the vector profile.

DIGITAL TEST WAVEFORMS

Digital test waveforms can be used in the digital processing block

instead of the ADC output. To enable digital test waveforms,

use Address 0x11B. Enable each channel individually in

Address 0x11A.

Waveform Generator

For testing and debugging, use a programmable waveform

generator in place of ADC data. The waveform generator can

vary offset, amplitude, and frequency. The generator uses the

ADC sample frequency, fSAMPLE, and ADC full-scale amplitude,

AFULL-SCALE, as references. The values are set in Address 0x117,

Address 0x118, and Address 0x119 (see Table 31).

x = C + A × sin(2 × π × N)

(8)

SAMPLE 



, see Address 0x117

(9)

SCALE

FULL





, see Address 0x118

(10)

C = AFULL-SCALE × a × 2−(13 − b), see Address 0x119

(11)

Channel ID and Ramp Generator

In Channel ID test mode, the output is a concatenated value.

Bits[6:0] are a ramp. Bit 7 is reserved as 0. Bits[10:8] are the

channel ID such that Channel A is coded as 000 and Channel B

is 001. Bits[15:11] are the chip address.

–60

020

FREQUENCY (MHz)

–50

–40

–30

–20

–10

LOW BAND FILTER

HIGH BAND FILTER

–8

020

FREQUENCY (MHz)

LOW BAND FILTER

HIGH BAND FILTER

–7

–6

–5

–4

–3

–2

–1

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