SSD1850 datasheet(31/56 Pages) ETC

31 / 56 page

SSD1850/51 Series

Rev 1.2

01/2003

SOLOMON

Read Status Byte

A 8 bits status byte will be placed onto the data bus when a read operation is performed if D/ C is low.

The status byte is defined as following:

Comment

BUSY

RES

DS1

DS0

BUSY=0 : Chip is idle

BUSY=1 : Chip is executing

instruction

ON=0 : Display is OFF

ON=1 : Display is ON

RES

=0: Chip is idle

RES

=1: Chip is executing reset

DS1, DS0 = 00: SSD1850

DS1, DS0 = 01: SSD1851

Data Read / Write

To read data from the GDDRAM, input High to R/W( WR ) pin and D/ C pin for 6800-series parallel mode,

Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial

mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after

each data read. Also, a dummy read is required before the first data is read. See P.14, Figure 4 in

Functional Description.

To write data to the GDDRAM, input Low to R/W( WR ) pin and High to D/ C pin for 6800-series parallel

mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be

increased by one automatically after each data write. After the data read/write operation (address=127) is

executed, the address will be reset to 0 in next data read/write operation.

Address Increment Table (Automatic)

D/ C

R/W( WR )

Action

Auto Address Increment

Write Command

Read Status

Write Data

Yes

Read Data

Yes

Address Increment is done automatically after data read/write. The column address pointer of GDDRAM

is affected. After the data read/write operation (address=127) is executed, the address will be reset to 0 in

next data read/write operation.

Commands Required for R/W ( WR ) Actions on RAM

W ( WR ) Actions on RAMs

Commands Required

Read/Write Data from/to

GDDRAM.

Set GDDRAM Page Address

Set GDDRAM Column Address

Read/Write Data

(1011X3X2X1X0)*

(0001X3X2X1X0)*

(0000X3X2X1X0)*

(X7X6X5X4X3X2X1X0)

* No need to resend the command again if it is set previously.

The read / write action to the Display Data RAM does not depend on the display mode. This means the

user can change the RAM content whether the target RAM content is being displayed or not.

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