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HT66F005 Datasheet(PDF) 75 Page - Holtek Semiconductor Inc |
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HT66F005 Datasheet(HTML) 75 Page - Holtek Semiconductor Inc |
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75 / 109 page  Rev. 1.30 �4 ���i� ��� �01� Rev. 1.30 �5 ���i� ��� �01� HT66F005/HT66F006 Cost-Effective A/D Flash MCU with EEPROM HT66F005/HT66F006 Cost-Effective A/D Flash MCU with EEPROM ACER Register Bit 7 6 5 4 3 2 1 0 Name — — — — �CE3 �CE� �CE1 �CE0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit7~4 Unimplemented,readas"0" Bit3 ACE3:DefinePA3isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN3 Bit2 ACE2:DefinePA2isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN2 Bit1 ACE1:DefinePA1isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN1 Bit0 ACE0:DefinePA0isA/Dinputornot 0:NotA/Dinput 1:A/Dinput,AN0 A/D Operation TheSTARTbitintheADCR0registerisusedtostartandresettheA/Dconverter.Whenthe microcontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversion cyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,the EOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset. ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigital converter. TheEOCBbitintheADCR0registerisusedtoindicatewhentheanalogtodigitalconversion processiscomplete.Thisbitwillbeautomaticallysetto0bythemicrocontrollerafteraconversion cyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterrupt controlregister,andiftheinterruptsareenabled,anappropriateinternalinterruptsignalwillbe generated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/D internalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontroller canbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasan alternativemethodofdetectingtheendofanA/Dconversioncycle. TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen tobeeitherfSYSorasubdividedversionoffSYS.Thedivisionratiovalueisdeterminedbythe ADCK2~ADCK0bitsintheADCR1register. AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCK2~ADCK0, therearesomelimitationsontheA/Dclocksourcespeedrangethatcanbeselected.Asthe recommendedrangeofpermissibleA/Dclockperiod,tADCK,isfrom0.5µsto10µs,caremustbe takenforselectedsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequency of4MHz,theADCK2~ADCK0bitsshouldnotbesetto000Bor110B.DoingsowillgiveA/D clockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/D clockperiodwhichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtablefor examples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,special caremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod. |
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