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SL28541BZCT Datasheet(PDF) 12 Page - Silicon Laboratories

Part # SL28541BZCT
Description  Clock Generator for Intel짰Mobile Chipset
PDF  31 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL28541BZCT Datasheet(HTML) 12 Page - Silicon Laboratories

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SL28541
...................... DOC #: SP-AP-0063 (Rev. AA) Page 12 of 31
Byte 8: Control Register 8
Bit
@Pup
Name
Description
7
1
Device_ID3
0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN
0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
0111 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
1000 = Reserved
1001 = CY28548
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
6
0
Device_ID2
5
0
Device_ID1
4
0
Device_ID0
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
1
27M_NSS_OE
Output enable for 27M_NSS
0 = Output Disabled, 1 = Output Enabled
0
1
27M_SS_OE
Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
Byte 9: Control Register 9
Bit
@Pup
Name
Description
7
0
PCIF_0_with PCI_STP#
Allows control of PCIF_0 with assertion of PCI_STP#
0 = Free running PCIF, 1 = Stopped with PCI_STP#
6
HW
TME_STRAP
Trusted mode enable strap status
0 = Normal, 1 = No overclocking
5
1
REF_DSC1
REF drive strength 1 of 2 (See Byte 17 and 18 for more setting)
0 = Low, 1 = High
4
0
TEST_MODE_SEL
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
3
0
TEST_MODE_ENTRY
Allow entry into test mode
0 = Normal operation, 1 = Enter test mode
2
1
I2C_VOUT<2>
Differential Amplitude Configuration
I2C_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 082V
100 = 0.86V
101 = 0.90V (default)
110 = 0.93V
111 = unused
1
0
I2C_VOUT<1>
0
1
I2C_VOUT<0>
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
HW
GCLK_SEL latch
Readback of GCLK_SEL latch
0 = DOT96/LCD_100, 1 = SRC0/27 MHz
6
1
PLL3_EN
PLL3 power down
0 = Power down, 1 = Power up



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