SL28541BZCT datasheet(17/31 Pages) SILABS

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SL28541

...................... DOC #: SP-AP-0063 (Rev. AA) Page 17 of 31

Default = 0, (0000). The allowable values for N are detailed

in Table 1, Frequency Select Table.

• CPU DAF M – There are 7 bits (for 128 values) to linearly

change the CPU frequency (limited by VCO range). Default

= 0, the allowable values for M are detailed in Table 1,

Frequency Select Table

• SRC_DAF Enable – This bit enables SRC DAF mode. By

default, it is not set. When set, the operating frequency is

determined by the values entered into the SRC_DAF_N

valid values before SRC_DAF is set. Default = 0, (No DAF).

• SRC_DAF_N – There are nine bits (for 512 values) to

linearly change the CPU frequency (limited by VCO range).

Default = 0, (0000). The allowable values for N are detailed

in Table 1, Frequency Select Table.

Smooth Switching

The device contains one smooth switch circuit that is shared

by the CPU PLL and SRC PLL. The smooth switch circuit

ensures that when the output frequency changes by

overclocking, the transition from the old frequency to the new

frequency is a slow, smooth transition containing no glitches.

The rate of change of output frequency when using the smooth

switch circuit is less than 1 MHz/0.667

s. The frequency

overshoot and undershoot is less than 2%.

The Smooth Switch circuit assigns auto or manual. In Auto

mode, clock generator assigns smooth switch automatically

when the PLL does overclocking. For manual mode, assign

the smooth switch circuit to PLL via Smbus. By default the

smooth switch circuit is set to auto mode. PLL can be

over-clocked when it does not have control of the smooth

switch circuit but it is not guaranteed to transition to the new

frequency without large frequency glitches.

Do not enable over-clocking and change the N values of both

PLLs in the same SMBUS block write and use smooth switch

mechanism on spread spectrum on/off.

PD_RESTORE

If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PD# LOW,

the SL28541 initiates a full reset. The result of this is that the

clock chip emulates a cold power on start and goes to the

“Latches Open” state. If the PD_RESTORE bit is set to a ‘1’

then the configuration is stored upon PD# asserted LOW. Note

that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the

PD_RESTORE bit must be ignored. In other words, in Intel

iAMT mode, PD# reset is not allowed.

PD# (Power down) Clarification

The CKPWRGD/PD# pin is a dual-function pin. During initial

power up, the pin functions as CKPWRGD. Once CKPWRGD

has been sampled HIGH by the clock chip, the pin assumes

PD# functionality. The PD# pin is an asynchronous active

LOW input used to shut off all clocks cleanly before shutting

off power to the device. This signal is synchronized internally

to the device before powering down the clock synthesizer. PD#

is also an asynchronous input for powering up the system.

When PD# is asserted LOW, clocks are driven to a LOW value

and held before turning off the VCOs and the crystal oscillator.

PD# (Power down) Assertion

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and differential clocks must held

LOW. When PD mode is desired as the initial power on state,

PD must be asserted HIGH in less than 10

s after asserting

CKPWRGD.

PD# Deassertion

The power up latency is less than 1.8 ms. This is the time from

the deassertion of the PD# pin or the ramping of the power

supply until the time that stable clocks are generated from the

clock chip. All differential outputs stopped in a three-state

condition, resulting from power down are driven high in less

than 300

s of PD# deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

each clock. Figure 2 is an example showing the relationship of

clocks coming up.

PD#

USB, 48MHz

DOT96T

DOT96C

SRCT 100MHz

SRCC 100MHz

CPUT, 133MHz

PCI, 33 MHz

REF

CPUC, 133MHz

Figure 1. Power down Assertion Timing Waveform

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