CYW43353 datasheet(13/113 Pages) CYPRESS

13 / 113 page

Document No. 002-14949 Rev. *F

Page 13 of 113

PRELIMINARY

CYW43353

During each clock cycle, the PMU sequencer performs the following actions:

■ Computes the required resource set based on requests and the resource dependency table.

■ Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource

and inverts the ResourceState bit.

■ Compares the request with the current resource status and determines which resources must be enabled or disabled.

■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.

■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.

2.5 Power-Off Shutdown

The CYW43353 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices

in the system, remain operational. When the CYW43353 is not needed in the system, VDDIO_RF and VDDC are shut down while

VDDIO remains powered. This allows the CYW43353 to be effectively off while keeping the I/O pins powered so that they do not

draw extra current from any other devices connected to the I/O.

During a low-power shut-down state, the provided VDDIO remains applied to the CYW43353, all outputs are tristated, and most

input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current

paths or create loading on any digital signals in the system, and enables the CYW43353 to be fully integrated in an embedded

device and take full advantage of the lowest power-savings modes.

When the CYW43353 is powered on from this state, it is the same as a normal power-up, and the device does not retain any infor-

mation about its state from before it was powered down.

2.6 Power-Up/Power-Down/Reset Circuits

The CYW43353 has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator

blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences,

see Section 19.: “Power-Up Sequence and Timing”.

Table 1. Power-Up/Power-Down/Reset Control Signals

Signal

Description

WL_REG_ON

This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the BT_REG_ON

input to control the internal CYW43353 regulators. When this pin is high, the regulators are enabled and the WLAN section

is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the

regulators are disabled. This pin has an internal 200 k

 pull-down resistor that is enabled by default. It can be disabled

through programming.

BT_REG_ON

This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal CYW43353

regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k

 pull-

down resistor that is enabled by default. It can be disabled through programming.

CYW43353 Datasheet(PDF) 13 Page - Cypress Semiconductor