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MB91F467BA Datasheet(PDF) 45 Page - Cypress Semiconductor |
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MB91F467BA Datasheet(HTML) 45 Page - Cypress Semiconductor |
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45 / 127 page  MB91460B Series Document Number: 002-04608 Rev. *A Page 44 of 126 9.3.2 Flash Access Timing Settings in CPU mode The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) for Flash read and write access. 9.3.2.1 Flash Read Timing Settings (Synchronous Read) 9.3.2.2 Flash Write Timing Settings (Synchronous Write) Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark to 24 MHz 0 0 0 - 1 to 48 MHz 0 0 1 - 2 to 96 MHz 1 1 3 - 4 to 100 MHz 1 1 3 - 4 not available on MB91F467BA/MB91F466BA Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark to 16 MHz 0 - - 0 3 to 32 MHz 0 - - 0 4 to 48 MHz 0 - - 0 5 to 64 MHz 1 - - 0 6 to 96 MHz 1 - - 0 7 to 100 MHz 1 - - 0 7 not available on MB91F467BA/MB91F466BA |
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