MB90347CEPF datasheet(66/93 Pages) CYPRESS

66 / 93 page

Document Number: 002-04498 Rev. *A

Page 65 of 92

MB90340E Series

11.4.9 LIN-UART0/1/2/3



Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0

(TA  40°C to 105°C, VCC  5.0 V  10, fCP 24 MHz, VSS  0 V)

Note:

 AC characteristic in CLK synchronized mode.

 C

L is load capacity value of pins when testing.

 t

CP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.

Parameter

Symbol

Condition

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCK0 to SCK3

Internal shift clock

mode output pins are

 80 pF  1 TTL.

5 tCP



SCK

  SOT delay time

tSLOVI

SCK0 to SCK3,

SOT0 to SOT3

50

50

Valid SIN

 SCK 

tIVSHI

SCK0 to SCK3,

SIN0 to SIN3

tCP + 80



SCK

  Valid SIN hold time

tSHIXI

SCK0 to SCK3,

SIN0 to SIN3



Serial clock “L” pulse width

tSHSL

SCK0 to SCK3

External shift clock

mode output pins are

 80 pF  1 TTL.

3 tCP - tR



Serial clock “H” pulse width

tSLSH

SCK0 to SCK3

tCP + 10



SCK

  SOT delay time

tSLOVE

SCK0 to SCK3,

SOT0 to SOT3



2 tCP + 60

Valid SIN

 SCK 

tIVSHE

SCK0 to SCK3,

SIN0 to SIN3



SCK

  Valid SIN hold time

tSHIXE

SCK0, SCK1,

SIN0 to SIN3

tCP + 30



SCK fall time

SCK0 to SCK3



SCK rise time

SCK0 to SCK3



SCK0 to SCK3

2.4 V

0.8 V

SOT0 to SOT3

0.8 V

2.4 V

0.8 V

tSLOVI

SIN0 to SIN3

VIL

VIH

VIL

VIH

tSCYC

tIVSHI

tSHIXI

 Internal Shift Clock Mode

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