MB90347CEPF datasheet(73/93 Pages) CYPRESS

73 / 93 page

Document Number: 002-04498 Rev. *A

Page 72 of 92

MB90340E Series

11.4.13 I2C Timing

(TA  –40C to +105C, VCC  5.0 V  10, VSS  0.0 V)

*1:For use at over 100 kHz, set the machine clock to at least 6 MHz.

*2:R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.

*3:The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.

*4:A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT  250 ns must then be

met.

Parameter

Symbol

Condition

Standard-mode

Fast-mode*1

Unit

Min

Max

Min

Max

SCL clock frequency

fSCL

 1.7 k,

 50 pF*2

100

400

kHz

Hold time (repeated) START condition

SDA

  SCL 

tHDSTA

4.0



0.6

s

“L” width of the SCL clock

tLOW

4.7



1.3

s

“H” width of the SCL clock

tHIGH

4.0



0.6

s

Set-up time (repeated) START condition

SCL

  SDA 

tSUSTA

4.7



0.6

s

Data hold time

SCL

  SDA  

tHDDAT

03.45*3

00.9*4

s

Data set-up time

SDA

   SCL 

tSUDAT

250



100



Set-up time for STOP condition

SCL

  SDA 

tSUSTO

4.0



0.6

s

Bus free time between a STOP and START condition

tBUS

4.7



1.3

s

SDA

SCL

tLOW

tSUDAT

tHDSTA

tBUS

tHDSTA

VIL

VIH

VIL

VIH

VIL VIL

VIL

VIH

tHDDAT

tHIGH

tSUSTA

tSUSTO

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