MB90347CEPF datasheet(24/93 Pages) CYPRESS

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Document Number: 002-04498 Rev. *A

Page 23 of 92

MB90340E Series

5. Handling Devices

1.Preventing latch-up

CMOS IC may suffer latch-up under the following conditions:



A voltage higher than VCC or lower than VSS is applied to an input or output pin.



A voltage higher than the rated voltage is applied between VCC and VSS pins.



The AVCC power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply

voltage.

2.Handling unused pins

Leaving unused input terminals open may lead to permanent damage due to malfunction and latch-up; pull up or pull down the

terminals through the resistors of 2 k

 or more.

3.Power supply pins (VCC/VSS)



If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected

inside of the device to prevent malfunction such as latch-up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the

standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.

Connect VCC and VSS pins to the device from the current supply source at a possibly low impedance.



As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1

F as a bypass capacitor

between VCC and VSS pins in the vicinity of VCC and VSS pins of the device.

4.Mode Pins (MD0 to MD2)

Connect the mode pins directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the

printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance

connection.

Vcc

Vss

Vcc

Vss

Vcc

MB90340E

Series

Vcc

Vss

Vcc

Vss

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